Semiconductor device and methods of manufacturing the same
a technology of mos transistor and semiconductor layer, which is applied in the direction of mos transistor, semiconductor device, electrical apparatus, etc., can solve the problems of high power consumption, change in the threshold voltage of mos transistor, and difficulty in optimizing the thickness of gate dielectric layer and channel ion implantation concentration, so as to prevent leakage current
Inactive Publication Date: 2005-07-14
SAMSUNG ELECTRONICS CO LTD
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- Abstract
- Description
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- Application Information
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Benefits of technology
[0007] The present invention is directed to an enhancement mode MOSFET based semiconductor device and a method of manufacturing the semiconductor device intended to prevent a leakage current from occurring due to a GIDL (Gate induced drain leakage) effect.
[0008] According to an embodiment of the present invention, there is provided a semiconductor device manufacturing method, which may prevent the leakage current from occurring due to the GIDL effect, comprising the steps of forming a first dielectric film on an entire upper part of a semiconductor substrate, forming a photoresist pattern on a p-well including a gate pattern of an NMOS transistor and a gate spacer thereof, and subsequently implanting ions into an n-well for forming a high concentration source / drain regions of a PMOS by using the first dielectric film formed on upper parts of a gate pattern and a gate spacer of a PMOS transistor as an implant mask, and forming an interlayer dielectric film thereon and then forming a contact, wherein said semiconductor substrate includes a PMOS transistor region in the n-well; an NMOS transistor region in the p-well, the gate pattern of the PMOS transistor formed on the PMOS transistor region and the gate spacers formed on both side walls of the gate pattern thereof, and the gate pattern of the NMOS transistor formed on the NMOS transistor region and the gate spacers formed on both side walls of the gate pattern thereof, the n-well having a low concentration source / drain regions formed by ion-implantation using the gate pattern of the PMOS transistor as an implant mask, and the p-well having a low concentration source / drain regions formed by ion-implantation using the gate pattern of the NMOS transistor as an implant mask and a high concentration source / drain regions formed by ion-implantation using the gate pattern and the gate spacers of the NMOS transistor as an implant mask.
Problems solved by technology
A high leakage current flow through the semiconductor device made of the MOS transistors, in the stand-by condition, leads to a high power consumption.
However, these conventional methods also cause a change in the threshold voltage of the MOS transistor, making it difficult to optimize the thickness of the gate dielectric layer and the channel ion implantation concentration.
Such a large leakage current may cause an error operation of a PMOS transistor.
Method used
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Embodiment Construction
[0020] Korean Patent Application No. 2002-51322, filed on Aug. 29, 2002, and entitled: “Semiconductor Device and Method of Manufacturing the Same”, is incorporated herein in its entirety.
[0021] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a la...
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A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source / drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source / drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source / drain regions.
Description
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates in general to a semiconductor device and a method of manufacturing the same. More particularly, the present invention is directed to an enhancement mode MOSFET device and methods of manufacturing the same. [0003] 2. Description of the Related Art [0004] Increasing the density of integration of a semiconductor device requires shortening of channel length of MOS transistors. If the channel length of the MOS transistor is shortened, a significant leakage current flows even though a voltage lower than a threshold voltage is applied to a gate of the MOS transistor. A high leakage current flow through the semiconductor device made of the MOS transistors, in the stand-by condition, leads to a high power consumption. Several methods, such as reducing the thickness of a gate dielectric layer or increasing the channel ion implantation concentration etc, have been tried for solving this short chan...
Claims
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IPC IPC(8): H01L27/092H01L21/265H01L21/336H01L21/8238H01L27/108H01L29/76H01L29/78
CPCH01L21/2652H01L21/823814H01L29/7833H01L21/823842H01L29/6659H01L21/823835H01L27/092
InventorSEO, SANG-HUNPARK, SEUNG-HYUNLEE, HAN-SINKIM, MOO-SUNGYANG, WON-SUK
OwnerSAMSUNG ELECTRONICS CO LTD