Memory control apparatus executing prefetch instruction

Abstract

A memory controller reads data from DRAM at a request from a plurality of masters. It includes a prefetch buffer for storing a result of a pre-reading operation, and a register for setting a specific master among a plurality of masters. When a master requests a read, the memory controller pre-reads data subsequent to the requested data, and determines whether or not the master is a specific master set by the register. If the master is the specific master set by the register, then the result of the pre-read is stored in the prefetch buffer. Thus, the prefetch buffer can effectively function in a system having a plurality of masters.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a memory control apparatus capable of executing a prefetch instruction. [0003] 2. Related Background Art [0004] Recently, the CPU speed seems boundless, and increases at an annual rate more than 1.5 times. In this connection, the amount of data transferred in a unit time between the CPU and main storage increases correspondingly. To relax this tendency, by using locality of memory access there has been the technology of increasing the capacity of cache provided in the CPU and configuring it in a hierarchical structure so that a high-speed memory access can be attained. However, it has become more and more difficult to solve the problem of an increasing gap between the operating speed of the CPU and the speed of access to the main storage. [0005] To efficiently solve this problem, it is necessary to drastically speeding up the access to the main storage (memory bandwidth) itself. Curr...

AI Technical Summary

Benefits of technology

[0031] The present invention aims at providing a memory controller capable of allowing a prefetch buffer having only a small entries to effectively function in a system including a plurality of bus masters.

Problems solved by technology

However, it has become more and more difficult to solve the problem of an increasing gap between the operating speed of the CPU and the speed of access to the main storage.

Therefore, access in size smaller than 32 bytes reduces an effective bandwidth.

However, if there are a plurality of bus masters, and they alternately access data at different address ranges, the contents of a prefetch buffer are frequently replaced before reference is made, thereby losing the significance of a prefetch buffer.

Thus, when a plurality of bus masters are simultaneously operating, the conventional memory controller cannot efficiently control a prefetch buffer having a small number of entries.

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