Error correction apparatus for performing consecutive reading of multiple code words

Abstract

An error correction apparatus for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words. The device includes a memory access circuit for controlling reading and writing of the code words to the buffer memory. Operational circuits perform a syndrome calculation with each of the multiple code words read from the buffer memory. The memory access circuit consecutively reads the multiple code words from the buffer memory and distributes the code words to the operational circuits.

Description

[0001] This application is a continuation and claims the benefit of priority under 35 USC § 120 of U.S. application Ser. No. 10 / 105,010, filed Mar. 22, 2002, which claims the benefit of a foreign priority application filed in Japan, serial number 2001-082298, filed Mar. 22, 2001. The disclosure of the the prior applications are considered part of (and are incorporated by reference in) the disclosure of this application.BACKGROUND OF THE INVENTION [0002] The present invention related to an error correction apparatus, and more particularly, to an error correction apparatus for calculating the syndrome of the data stored in a buffer memory, which includes a random access memory, to correct errors. [0003] FIGS. 1(a) to 1(d) illustrate the data format of a compact disc ROM (CD-ROM). As shown in FIG. 1(a), CD-ROM data is formed from multiple sectors, each of which has 2352 bytes. Each sector includes 12 bytes of synchronizing data, 4 bytes of a header, 2048 bytes of user data, 4 bytes of ...

AI Technical Summary

Benefits of technology

The present invention is an error correction apparatus and method for digital data stored in a buffer memory with multiple code words. The apparatus includes a memory access circuit for controlling reading and writing of the code words to the buffer memory, and multiple operational circuits performing a syndrome calculation with each code word. The apparatus generates an address signal to designate an address of the code words read from and written to the buffer memory, and a timing signal to control the address generation circuit so that the address signal is generated to read the code words. The apparatus also generates multiple syndromes in parallel in correspondence with the multiple code words by processing the code words of the digital data read from the buffer memory. The error correction process is performed on the digital data using the multiple syndromes. The technical effects of the invention include improved efficiency and accuracy in error correction processing for digital data stored in a buffer memory.

Problems solved by technology

This hinders with increasing the speed of the error correction process.

Such problem occurs in an error correction apparatus that stores data temporarily in a buffer memory and then sequentially reads symbols which performing error detection or error correction.

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