Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop

a technology of electroless co alloy and etch stop, which is applied in the direction of semiconductor/solid-state device manufacturing, basic electric elements, electric apparatus, etc., can solve the problems of oxidation related failure, device failure, and copper diffusion of cu interconnects, and achieve the effect of reducing oxide formation

Inactive Publication Date: 2007-05-03
APPLIED MATERIALS INC
View PDF22 Cites 28 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0009] The present invention generally provides method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. The present invention al

Problems solved by technology

However, despite the positive attributes of Cu, Cu interconnects are susceptible to copper diffusion, electromigration related failures, and oxidation related failures.
In particular, oxidation is particularly detrimental in thinner capping layers having thicknesses of less than about 150 Å, for example, a 70 Å layer of CoWP or CoWPB.
Specifically, if there is limited adhesion between the capping layer 22 and the dielectric layer 16, the capping layer 22 and dielectric layer 16 may delaminate, leading to device failure.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop
  • Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop
  • Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] Embodiments of the present invention generally pertain to a process of forming reliable interconnect layers to improve the adhesion between a capping layer and a subsequently deposited dielectric layer, which is desirable to improve final device performance. Hindering oxide formation along the surface of the capping layer helps improve adhesion and final device performance.

[0022]FIG. 2 is a sectional view of an embodiment of a formed feature. FIG. 2 illustrates a cross-sectional view of an interconnect 9 containing a conductive fill material 13 disposed within an interconnect opening with a barrier layer 12 formed in a dielectric material 14. In one embodiment, the dielectric material 14 is a low dielectric constant (low k) dielectric material, such as, a Black Diamond™ film, available from Applied Materials, Inc. of Santa Clara, Calif.; CORAL™ film, available from Novellus Systems Inc. of San Jose, Calif., AURORA™ film available from ASM International of Bilthoven, Netherla...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on a substrate, exposing the capping layer to a plasma, heating the substrate to more than about 100° C., and depositing a low dielectric constant material.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims benefit of U.S. provisional patent application Ser. No. 60 / 731,170 (APPM / 10658L / PPC / ELESS / CKIM), filed Oct. 28, 2005, which is herein incorporated by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] Embodiments of the present invention generally relate to a process of reliably forming devices on a semiconductor substrate. [0004] 2. Description of the Related Art [0005] Currently, copper and its alloys are the metals of choice for sub-micron interconnect technology because copper (Cu) has a low resistivity, a high current carrying capacity, and high electromigration resistance. However, despite the positive attributes of Cu, Cu interconnects are susceptible to copper diffusion, electromigration related failures, and oxidation related failures. Typically, a liner barrier layer is used to encapsulate the sides and bottom of the Cu interconnect to prevent diffusion of Cu to the adjacent d...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/469
CPCH01L21/76829H01L21/76843H01L21/76846H01L21/76849H01L21/76862H01L21/76864H01L21/76834
InventorFANG, HONGBINWEIDMAN, TIMOTHYMEI, FANGWANG, YAXINSHANMUGASUNDRAM, ARULKUMARBENCHER, CHRISTOPHER D.NAIK, MEHUL B.
OwnerAPPLIED MATERIALS INC