Semiconductor wafer and method for making the same
a technology of semiconductor integrated circuit chips and silicon oxide dielectrics, which is applied in the direction of semiconductor/solid-state device testing/measurement, semiconductor devices, semiconductor/solid-state device details, etc., can solve the problems of adhesion ability, performance degradation of ic chips, and almost all low-k dielectric materials possess relatively lower mechanical strength than that of conventional silicon oxide dielectrics such as fsg or usg, so as to achieve effective reinforcement structure
Inactive Publication Date: 2007-11-22
UNITED MICROELECTRONICS CORP
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Benefits of technology
[0008] It is therefore the primary object of the present invention to provide an effective reinforcing structure, which is disposed deliberately in and along two opposite sides of each WAT pad on a wafer in order to stop the propagation of interface de-lamination between low-k dielectric layers originated from the wafer dicing process.
Problems solved by technology
However, one shortcoming associated with the use of low-k dielectrics is that almost all low-k dielectric materials possess relatively lower mechanical strength than that of conventional silicon oxide dielectrics such as FSG or USG.
The use of low-k dielectrics poses this industry another problem that the adhesion ability, either at the interface between two adjacent low-k dielectric layers or at the interface between a low-k dielectric layer and a dissimilar dielectric layer, is inadequate to meet the requirements in the subsequent wafer treatment processes such as wafer dicing, which is typically performed to mechanically cut a semiconductor wafer into a number of individual IC chips.
It has been found that the so-called “interface de-lamination” phenomenon occurs between low-k dielectric layers during or after the wafer dicing process is performed, causing performance degradation of the IC chips.
Method used
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[0015] Please refer to FIGS. 1 and 2. FIG. 1 is an enlarged, schematic plan view of the dicing line between circuit chips of a semiconductor wafer in accordance with one preferred embodiment of this invention. FIG. 2 is a schematic cross section taken along line 1-1 of FIG. 1. As shown in FIG. 1, a semiconductor wafer 10 comprises two adjacent integrated circuit chips 12 and 14.
[0016] There is a dicing line 16 between the two adjacent integrated circuit chips 12 and 14. A plurality of wafer acceptance testing (WAT) pads 20 is formed in the dicing line 16. The WAT pads 20 are connected with corresponding test key circuits (not shown). According to the preferred embodiment, the dimension of the WAT pad 20 is about 50 micrometers.
[0017] The integrated circuit chips 12 and 14 are surrounded by die seal rings 12a and 14a, respectively. Within the integrated circuit chips 12 and 14, an active integrated circuit is fabricated. The active integrated circuit may comprise components such as...
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A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT pads has thereon a slot opening. A reinforcement structure is formed within the slot opening and penetrates through the WAT pad for stopping propagation of de-lamination during wafer dicing.
Description
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This is a division of U.S. application Ser. No. 11 / 277,149 filed Mar. 22, 2006.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to semiconductor integrated circuit devices and, more particularly, to the fabrication of semiconductor integrated circuit chips provided with a means of stopping propagation of interface de-lamination between dielectric layers originated from the wafer dicing process. [0004] 2. Description of the Prior Art [0005] Semiconductor manufacturers have been shrinking transistor size in integrated circuits (IC) to improve chip performance. This has resulted in increased speed and device density. For sub-micron technology, the RC delay becomes the dominant factor. To facilitate further improvements, semiconductor IC manufacturers have been forced to resort to new materials utilized to reduce the RC delay by either lowering the interconnect wire resistance, or b...
Claims
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IPC IPC(8): H01L21/304
CPCH01L22/34H01L23/585H01L2924/0002H01L2924/00
InventorWU, PING-CHANG
OwnerUNITED MICROELECTRONICS CORP