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Method of detecting and recovering a lost system management interrupt (SMI) in a multiprocessor (MP) environment

a multi-processor and interrupt technology, applied in the field of multi-processor system methods, can solve problems such as difficulties in handling multiple smi events, processors may lose smi,

Inactive Publication Date: 2008-11-06
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach effectively recovers and handles lost SMI events by ensuring all processors are in the SMI handler before proceeding, reducing latency and improving the handling of multiple SMI events in multiprocessor systems.

Problems solved by technology

If multiple SMI events are received when one or more processors are in SMI and one or more other processors are not in SMI, then certain processors may lose an SMI.
This causes a problem, because the processors remaining in the SMI handler need to process an SMI, but can't do so without all of the active processors in SMI.
Essentially, the latency between multiple processors entering and exiting SMM can cause difficulties in handling multiple SMI events.

Method used

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  • Method of detecting and recovering a lost system management interrupt (SMI) in a multiprocessor (MP) environment
  • Method of detecting and recovering a lost system management interrupt (SMI) in a multiprocessor (MP) environment
  • Method of detecting and recovering a lost system management interrupt (SMI) in a multiprocessor (MP) environment

Examples

Experimental program
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example 1

A Two Processor System. (Hypothetical)

[0029]A two processor system is the simplest multiprocessor system to discuss, yet allows for an adequate description of the methods of the present invention. However, the invention may be implemented in systems have any number of two or more processors.

[0030]In Table 1, a hypothetical sequence of events is set out in order from top to bottom. Some events have been illustrated as occurring in the same “step”, although this is merely an illustration and should not be taken as limiting. The Table illustrates the occurrence of SMI events and the corresponding status of first and second processors.

[0031]In Step 1, SMI Event 1 is issued and both processors enter the SMI handler for Event 1. In Step 2, SMI Event 1 is handled, because all of the processors are in the SMI handler for Event 1. Although not shown, one of the processors would have been selected to handle the SMI event. In step 3, Processor #1 exits the SMI Handler for Event 1, but Processo...

example 2

A Two Processor System Having a Selected Processor with a Pending SMI Event at the Time the Selected Processor Schedules a Further SMI Event. (hypothetical)

[0033]This example illustrates the importance that the processors exit the SMI handler before a scheduled SMI is issued. Steps 1 through 12 in Table 2 are the same as in Table 1 and the description of these steps will not be repeated here. The distinction between the two Tables begins at step 20 in Table 2.

[0034]In step 20, SMI Event 4 is issued before Processor #1 has timed out in step 21, scheduled a further SMI Event 5 in step 22, and exited SMI Event 4 in step 23. Accordingly, in step 20 Processor #1 keeps SMI Event 4 pending and Processor #2 enters SMI Event 4. Therefore, after exiting the SMI Event 3, Processor #1 enters pending SMI Event 4 in step 24. Because all of the processors are then in the SMI handler for Event 4, SMI Event 4 is handled in step 25 and both Processor #1 and Processor #2 exit SMI Event 4 in step 26. B...

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PUM

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Abstract

Method, computer program product and system for handling multiple system management interrupt (SMI) events in a multiprocessor system. In response to receiving an SMI event, processors enter system management mode (SMM) and execute SMI handler code. An SMI handler that determines fewer than all of the processor are in the SMI handler for the event will schedule an further SMI event based upon the content of the detected SMI event, then issues a resume (RSM) instruction and exits the SMI handler. The method recovers lost SMI events caused by latency between multiple processors entering or exiting SMM.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of and claims priority to co-pending U.S. patent application Ser. No. 11 / 531,740, filed on Sep. 14, 2006.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention is related to methods for handling system management interrupts in a multiprocessor system.[0004]2. Background of the Related Art[0005]Since the 386SL processor was introduced by the Intel Corporation, SMM has been available on IA32 processors as an execution mode hidden to operating systems that executes code loaded by BIOS or firmware. SMM is a special-purpose operating mode provided for handling system-wide functions like power management, system hardware control, or proprietary OEM-designed code. The execution mode is deemed “hidden” because the operating system (OS) and software applications cannot see it, or even access it.[0006]IA32 processors are enabled to enter SMM via activation of an SMI (System Managemen...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/52
CPCG06F13/24
Inventor SHAH, MEHUL MAHENDRABHAI
Owner INT BUSINESS MASCH CORP