Performance Evaluation of Algorithmic Tasks and Dynamic Parameterization on Multi-Core Processing Systems

Abstract

Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)[0001]The present application is related to a commonly assigned U.S. application entitled “Performance Evaluation of Algorithmic Tasks and Dynamic Parameterization on Multi-core Processing Systems,” identified by attorney docket number IN920070084US1, and filed on even date herewith, the disclosure of which is incorporated by reference herein in its entirety.FIELD OF THE INVENTION[0002]The present invention relates to the electrical, electronic, and computer arts, and, more particularly, to evaluating the performance of algorithmic tasks.BACKGROUND OF THE INVENTION[0003]A multi-core computing system typically includes some combination of shared memory units, accessible by all cores, and / or local memory units, associated with individual cores. Most of the cores, although not necessarily all, access these memory units using direct memory access (DMA). Access to local memory units may be direct and / or some cores may have direct access to the sha...

AI Technical Summary

Benefits of technology

[0012]An illustrative embodiment of the present invention meets the above-noted need by providing techniques for more efficiently evaluating the performance of algorithmic tasks on a target multi-core processing system. Results of a benchmark indicative of a measure of performance of a template characterizing an algorithmic task to be evaluated on a target multi-core processing system can be collected and stored. The stored performance results can be used to dynamically determine optimal performance parameters with which to schedule a task at run-time.

Problems solved by technology

Unfortunately, however, these conventional techniques work offline and generate optimal code for fixed configurations (Fast Fourier Transform in the West (FFTW), a C subroutine library, may work dynamically at run-time, but that is only useful if the plan (i.e., outcome) is to be reused multiple times; otherwise it is more beneficial to store and reuse the plan rather than run it every time).

Moreover, these techniques do not take into account optimizations possible with regards to DMA operations (e.g., they do not search the DMA parameter space).

Some of the issues involved include the following:DMA operations tend to have high latencies, discouraging working iteratively on small blocks / vectors.Performance of DMA lists is often not as good as that of contiguous DMA.

In single-ported local memory units, the DMA operations can undesirably interfere with the computation, thereby impacting the performance of the algorithmic task(s) being performed (for instance, the core could starve for instructions if DMA is given higher priority than the local memory unit).

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