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Semiconductor device with buried gate and method for fabricating the same

a semiconductor device and buried gate technology, applied in the direction of semiconductor devices, basic electric elements, electrical appliances, etc., can solve the problems of reducing the size of semiconductor devices, reducing the efficiency of manufacturing processes, so as to increase the process margins

Inactive Publication Date: 2012-06-21
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device with buried gates that improve the process margin of a storage node contact plug formation process, prevent shorts between storage node contact plugs and landing plugs under bit lines, and improve the contact margin of storage node contact plugs. The semiconductor device includes a substrate, a first layer, a first pattern, a second layer, a second pattern, a conductive layer, and storage node contact plugs. The method for fabricating the semiconductor device includes forming buried gates, a first layer, a first pattern, a second layer, a second pattern, a conductive layer, and storage node contact plugs. The technical effects of the present invention are improved process margin, prevention of shorts, and improved contact margin.

Problems solved by technology

As the size of semiconductor devices shrinks, compliance with diverse device characteristics and designing appropriate fabrication processes become more difficult.
Even if such small structures can be formed, desired device characteristics may not be obtained.

Method used

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  • Semiconductor device with buried gate and method for fabricating the same
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  • Semiconductor device with buried gate and method for fabricating the same

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Embodiment Construction

[0019]Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

[0020]The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third laye...

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Abstract

A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority of Korean Patent Application No. 10-2010-0128045, filed on Dec. 15, 2010, which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a semiconductor device with buried gates (BG) and a method for fabricating the same.[0003]As the size of semiconductor devices shrinks, compliance with diverse device characteristics and designing appropriate fabrication processes become more difficult. For example, in using 40 nm design rules, formation of structures of gates, bit lines, and contacts is reaching limits. Even if such small structures can be formed, desired device characteristics may not be obtained. To address such features, buried gate (BG) structures having gates buried in a substrate are used.[0004]FIGS. 1A and 1B illustrate a convent...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/78H01L21/28H10B12/00
CPCH01L21/76816H01L27/10855H01L21/76879H01L27/10894H01L21/28008H01L27/10876H10B12/053H10B12/09H10B12/0335H01L29/4236
Inventor SHIN, JONG-HANPARK, BO-MIN
Owner SK HYNIX INC