Unlock instant, AI-driven research and patent intelligence for your innovation.

Stacked semiconductor chips packaging

a technology of semiconductor chips and packaging, applied in the field of semiconductor chip processing, can solve the problems that the fabrication of these electoral interfaces may be particularly difficult in a stacking dice arrangemen

Inactive Publication Date: 2012-08-02
ADVANCED MICRO DEVICES INC
View PDF8 Cites 12 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a method of manufacturing a stack of substrates that includes a semiconductor chip. The method includes forming conductive vias in the chip and coupling them to corresponding conductor pads on a circuit board. The conductive vias have a first end in the chip and a second end that projects out of the chip. The technical effect of this invention is to provide a reliable and efficient way to connect semiconductor chips to other components in a circuit board, which can improve performance and reliability of the overall circuit.

Problems solved by technology

A technical challenge associated with most mounting schemes is the establishment of electrical interfaces between the semiconductor die or dice and the receiving circuit board.
The fabrication of these electoral interfaces may be particularly challenging in a stacked dice arrangement.
Expenses in the form of material and labor costs are associated with the conventional copper pillar process.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Stacked semiconductor chips packaging
  • Stacked semiconductor chips packaging
  • Stacked semiconductor chips packaging

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0009]In accordance with one aspect of the present invention, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.

[0010]In accordance with another aspect of the present invention, a method of manufacturing is provided that includes providing a circuit board that includes an outermost surface and plural conductor pads. A solder structure is formed on each of the plural conductor pads. Each of the solder structures includes a portion projecting beyond the outermost surface. The solder structures are coupled to corresponding conductive vias of a stack of substrates. At least one of the substrates is a semiconductor chip.

[0011]In accordance with another aspect of the pr...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for stacking multiple semiconductor devices and packaging the same.[0003]2. Description of the Related Art[0004]Some time ago semiconductor chip designers began stacking multiple semiconductor dice (aka “dies”) vertically in order to obtain more functionality without an attendant increase in required package substrate or circuit board area. A variety of techniques have been used to electrically connect adjacent dice in such stacked arrangements. One technique has involved the use of wire bonds leading from contact pads on one die to corresponding contact pads on an adjacent die. Another technique that has been introduced more recently involves the use of so-called thru-silicon-vias (TSV). A typical TSV is a conductive via that extends nearly or perhaps entirely through a semiconductor chip, depending on the prese...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/498H01L23/48H01L21/50
CPCH01L21/76898H01L25/0657H01L25/50H01L2225/06513H01L2225/06517H01L2225/06541H01L2924/01322H01L2924/15311H01L23/481H01L2224/73204H01L2924/00H01L21/4853H01L21/486H01L23/49811H01L23/49827H01L23/49838H01L25/073
Inventor FU, LEIKUECHENMEISTER, FRANK GOTTFRIEDSU, MICHAEL ZHUOYING
Owner ADVANCED MICRO DEVICES INC