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Data acquisition system for test and measurement signals

a data acquisition and data technology, applied in the field of data acquisition systems for test and measurement signals, can solve the problems of difficult processing and display of such high-rate data, and achieve the effect of facilitating the provision of pointers

Inactive Publication Date: 2013-04-18
C SPEED
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides an improved system for acquiring test and measurement data. It can sample input signals up to 2 GS / s using an FPGA, which was previously limited to 1 GS / s. The system can also downsample and compress data for faster recording and analysis. It automatically selects the most relevant data for display to the user and enables simultaneous acquisition and readout from memory. The system includes a computer system that reconfigures the FPGA to different modes and can transfer current settings to the acquisition device for seamless reconfiguration without disrupting user operation. Overall, the invention allows for faster, more efficient data acquisition and analysis.

Problems solved by technology

One drawback of viewing high rate signals is that readout, processing, and display of such high rate data is difficult with communication bandwidth bottlenecks between the acquisition device and the host computer system and hardware limitations of the host computer system.

Method used

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  • Data acquisition system for test and measurement signals
  • Data acquisition system for test and measurement signals
  • Data acquisition system for test and measurement signals

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Embodiment Construction

[0035]Referring to FIGS. 1 and 2, the system 10 of the present invention has an acquisition device 12, which receives multiple channels of electrical signals having amplitude or value over time from a device (unit or system) 14 under test, via test leads 15, and converts each of the electrical signals into digital data utilizing a front end 15a and a processing unit provided by an FPGA (field programmable gate array) 16 for storage in memory 18. A controller 17 in the acquisition device 12 provides an interface between the FPGA 16 and a host computer system 20, whereby computer system 20 may request data stored in memory 18 and controller 17 provides readout 22 of such data requested. The computer system 20 stores the received data in its memory (RAM or hard / optical drive) for rendering of the data by the computer system on display 24. Computer system 20 may represent a personal computer, work station, laptop computer, or other microprocessor based platform that is coupled to displa...

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Abstract

A system having an acquisition device for acquiring test and measurement data. For each input data signal, the acquisition device has two differential receivers of opposite polarity each having an output coupled to the input of different ones of two pairs of registers, resulting in four registers sampling the input data signal periodically at four different times in accordance with two clocking signals of different phase (phase shifted) 90° to provide a sampling rate four times the rate of the clocking signals. The resulting sample data is stored in memory along with downsampled data. A computer system can request readout of stored sample data and / or downsampled data during or after acquisition of sample data and downsampled data. The acquisition device preferably utilizes an FPGA to provide sampling, storage and readout of stored data. The FPGA may be reconfigurable to provide one of different data acquiring modes selectable by a user.

Description

Description[0001]1. Field of the Invention[0002]This present invention relates to a system (method) for acquisition of test and measurement data and reading out the acquired data to a computer system, and relates particularly to a system for acquisition of test and measurement data capable of sampling up to a 2 Gigasamples per second (GS / s) input signal using a clock operating at 500 MHz. The invention is particularly suitable with a Virtex-4 family FPGA manufactured by Xilinx, Inc. of San Jose, Calif. Heretofore such Virtex-4 family FPGA with a clock speed of 500 MHz per second was configurable to acquire data rates only as high as 1 GS / s, while the present invention enables use of the same FPGA to achieve acquisition rates of 2 GS / s (i.e., 4×500 MHz clock speed). In addition, at the same time of acquisition of the sample data the acquisition device produces and stores in its memory downsampled data representing a compressed version of the sample data which records detected togglin...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F15/00
CPCG06F15/00G01R13/0272
Inventor LOUISE, JUSTIN RALPHFRANCIS, KEVIN ROYHARRY, BRIAN DAVIDSHEPARDSON, BRYAN THOMAS
Owner C SPEED