Semiconductor device having plural semiconductor chips

Abstract

Disclosed herein is a device that including a first chip having first to fourth terminals and a second chip having fifth to seventh terminals. The first chip further includes a penetration electrode connected between the first and fourth electrodes and a first internal node coupled to of which an electrical potential being changed in response to an electrical potential of the first terminal. The second chip further includes a second internal node coupled to of which an electrical potential being changed in response to an electrical potential of the fifth terminal. The first internal node is electrically coupled to both the second terminal and the sixth terminal. The second internal node is electrically coupled to both the third terminal and the seventh terminal.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of semiconductor chips.[0003]2. Description of Related Art[0004]In recent years, a semiconductor device of a stacked type has been well known. A semiconductor device of a stacked type includes a plurality of semiconductor chips that employ a plurality of penetration electrodes. The plurality of semiconductor chips are electrically connected via the penetration electrodes. According to this configuration, a plurality of the semiconductor chips can be packaged on the circuit substrate in high density.[0005]Such a stacked semiconductor device needs to be tested whether input terminals of the semiconductor chips for signals to be supplied in common are electrically connected to outside properly.[0006]In recent years, the number of input terminals of individual semiconductor chips in a stacked semicondu...

AI Technical Summary

Benefits of technology

The semiconductor device described in this patent has two chips stacked together. The first chip has first and second terminals, while the second chip has third and fourth terminals. The first chip's internal node changes its electrical potential in response to the first terminal's potential. The second chip's internal node changes its electrical potential in response to the third and fourth terminals' potential. By connecting these internal nodes, the chips can communicate with each other. This design allows for more efficient data transfer between the chips.

Problems solved by technology

In other words, there has conventionally been a problem that input terminals that are connected to input terminals of other chips and therefore not capable of direct electrical contact and are not subjected to the boundary scan test method cannot be tested whether electrically connected to outside.

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