Method to achieve true fail safe compliance and ultra low pin current during power-up sequencing for mobile interfaces

Abstract

An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

Description

TECHNICAL FIELD[0001]Embodiments of the disclosure relate generally to integrated circuits (ICs) and more particularly to controlling PAD current or pin current during power-up sequence or power-down sequence in the integrated circuits.BACKGROUND[0002]The ever-increasing complexity and performance requirements of portable media devices call for effective system-level power management in Integrated circuits (ICs). Having one or more Switchable Power-Domains in Core-logic is a well-known low-power methodology that is employed for ICs in portable media devices. When a supply of a specific Power Domain is powered down, the outputs of that power-domain serving as inputs to IO (input / output) circuits are no longer valid and these IO circuits need to be tristated to avoid possible leakage current. An IO circuit drive / receive signals on a PAD to interface with the outside world. If the IO circuit is not properly tristated, it results in high leakage currents (conduction currents) from the P...

AI Technical Summary

Benefits of technology

[0018]FIG. 8(a) is an example graph illustrating the response of a cont

Problems solved by technology

If the IO circuit is not properly tristated, it results in high leak

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