Achieving Low Grace Period Latencies Despite Energy Efficiency
a grace period and energy efficiency technology, applied in the field of computer systems and methods, can solve the problems of increasing grace period latencies, burdensome read-side lock acquisition, and sleeping with callbacks, and cannot take full advantage of subsequent grace periods
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[0047]Turning now to the figures, wherein like reference numerals represent like elements in all of the several views, FIG. 4 illustrates an example multiprocessor computer system in which the grace period processing technique described herein may be implemented. In FIG. 4, a computer system 2 includes multiple processors 41, 42 . . . 4n, a system bus 6, and a program memory 8. There are also cache memories 101, 102 . . . 10n and cache controllers 121, 122 . . . 12n respectively associated with the processors 41, 42 . . . 4n. A conventional memory controller 14 is associated with the memory 8. As shown, the memory controller 14 may reside separately from processors 42 . . . 4n (e.g., as part of a chipset). As discussed below, it could also comprise plural memory controller instances residing on the processors 41, 42 . . . 4n.
[0048]The computer system 2 may represent any of several different types of computing apparatus. Such computing apparatus may include, but are not limited to, g...
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