Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Abstract

Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

Description

FIELD OF THE INVENTION[0001]Embodiments of the present invention relate generally to the manufacture of semiconductor devices. In particular, embodiments of the present invention relate to low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices.BACKGROUND AND RELATED ARTS[0002]As microprocessors become faster and smaller, integrated circuitry (IC) becomes more complex and components become more densely packed. Interconnect lines are needed to provide electrical connections to different portions of the device. The current patterning technique for forming interconnect lines includes the formation of trenches that have a uniform depth, as shown in FIG. 1. Conductive material is then disposed into the trenches to form interconnect lines 120. However, as the pitch of the interconnect lines decrease, increases in the line-to-line capacitances between neighboring interconnect lines becomes a limiting factor. Prior attempts to decrease th...

AI Technical Summary

Benefits of technology

The present invention relates to a method for manufacturing semiconductor devices with low capacitance interconnect structures. The invention reduces the line-to-line capacitance in the interconnect structure by recessing alternating interconnect lines. This reduces the demand for precise alignment of masks and etching processes, which can improve the formation of isolated connections. The invention also utilizes dielectric materials with high selectivity over each other during an etching process to form more forgiving contact openings. The technical effects of the invention include reducing the line-to-line capacitance and improving the formation of isolated connections.

Problems solved by technology

As microprocessors become faster and smaller, integrated circuitry (IC) becomes more complex and components become more densely packed.

However, as the pitch of the interconnect lines decrease, increases in the line-to-line capacitances between neighboring interconnect lines becomes a limiting factor.

However, these approaches are limited by material properties and generally result in poor structural integrity.

In addition to the increase in the line-to-line capacitance, shrinking the pitch of the interconnect lines increases the demands on masking and etching processes required for the formation of connections to the interconnect lines from subsequent layers.

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