Vertical memory devices

a technology of vertical memory and memory device, which is applied in the direction of semiconductor devices, semiconductor device details, semiconductor/solid-state device details, etc., can solve the problems that the structural and electrical reliability of various structures included in vertical memory device may not be easily achieved, and achieve the effect of improving mechanical and electrical reliability

Inactive Publication Date: 2017-04-13
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0007]Example embodiments provide a vertical memory device having improved mechanical and electrical reliability.

Problems solved by technology

Thus, structural and electrical reliability of various structures included in vertical memory device may not be easily achieved.

Method used

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  • Vertical memory devices
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Examples

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Embodiment Construction

[0058]Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. Inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this description will be thorough and complete, and will fully convey the scope of inventive concepts to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference characters and / or numerals in the drawings denote like elements, and thus their description may not be repeated.

[0059]It will be understood that when an element or layer is referred to as being “on,”“connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present...

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Abstract

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This U.S. Non-Provisional application claims priority under 35 USC §119 to U.S. Provisional Application No. 62 / 240,660 filed on Oct. 13, 2015 in the USPTO, and Korean Patent Application No. 10-2015-0185178 filed on Dec. 23, 2015 in the Korean Intellectual Property Office (KIPO). The entire contents of the above-referenced applications are incorporated by reference herein.BACKGROUND[0002]1. Field[0003]Example embodiments relate to vertical memory devices. More particularly, example embodiments relate to vertical memory devices including vertically stacked gate lines.[0004]2. Description of Related Art[0005]Recently, a vertical memory device including a plurality of memory cells stacked vertically with respect to a surface of a substrate has been developed for achieving a high degree of integration. In the vertical memory device, a channel having a pillar shape or a cylindrical shape may protrude vertically from the surface of the substrate,...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/115H01L23/528
CPCH01L27/11582H01L27/11565H01L23/5283H10B43/10H10B43/35H10B43/27
Inventor PARK, JOO-HEELEE, JONG-MINKIM, SEON-KYUNGRHO, KEE-JEONGSHIN, JIN-HYUNPARK, JONG-HYUNWON, JIN-YEON
Owner SAMSUNG ELECTRONICS CO LTD
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