Vertical memory devices

Abstract

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This U.S. Non-Provisional application claims priority under 35 USC §119 to U.S. Provisional Application No. 62 / 240,660 filed on Oct. 13, 2015 in the USPTO, and Korean Patent Application No. 10-2015-0185178 filed on Dec. 23, 2015 in the Korean Intellectual Property Office (KIPO). The entire contents of the above-referenced applications are incorporated by reference herein.BACKGROUND[0002]1. Field[0003]Example embodiments relate to vertical memory devices. More particularly, example embodiments relate to vertical memory devices including vertically stacked gate lines.[0004]2. Description of Related Art[0005]Recently, a vertical memory device including a plurality of memory cells stacked vertically with respect to a surface of a substrate has been developed for achieving a high degree of integration. In the vertical memory device, a channel having a pillar shape or a cylindrical shape may protrude vertically from the surface of the substrate,...

AI Technical Summary

Benefits of technology

This patent is about a new type of vertical memory device that is more reliable than current options. It has improved mechanical and electrical reliability.

Problems solved by technology

Thus, structural and electrical reliability of various structures included in vertical memory device may not be easily achieved.

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