Self-Aligned Interconnection Structure and Method

Abstract

The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.

Description

PRIORITY DATA[0001]The present application is a divisional application of U.S. application Ser. No. 14 / 928,916, filed Oct. 30, 2015, which is hereby incorporated by reference in its entirety.BACKGROUND[0002]In semiconductor technology, an integrated circuit pattern can be defined on a substrate using a photolithography process. Dual damascene processes are utilized to form multilayer copper interconnections including vertical interconnection vias / contacts and horizontal interconnection metal lines. During a dual damascene process, a plug filling material is employed to fill in the vias (or contacts) and the material is then polished back. However, the vias (or contacts) are defined by a different lithography process and may cause misalignments between the underlying metal lines and the vias. Especially, when the semiconductor technologies move forward to advanced technology nodes with smaller feature sizes, such as 20 nm, 16 nm or less, the misalignments have less tolerance and may ...

AI Technical Summary

Benefits of technology

The present patent application is a divisional application of U.S. patent application Ser. No. 14 / 928,916, filed Oct. 30, 2015. The patent text describes a method and structure for making an integrated circuit (IC) using a dual damascene process. The technical effect of the patent is to address misalignments between vias and metal lines caused by misaligned pluggable materials and improve the tolerance of shorts, openings, and other issues in advanced technology nodes with smaller feature sizes. The method includes steps of forming a substrate, depositing a photoresist, and performing various fabrication stages to create the IC structure. The patent also includes various data associated with the integrated circuit structure.

Problems solved by technology

However, the vias (or contacts) are defined by a different lithography process and may cause misalignments between the underlying metal lines and the vias.

Especially, when the semiconductor technologies move forward to advanced technology nodes with smaller feature sizes, such as 20 nm, 16 nm or less, the misalignments have less tolerance and may cause short, opening or other issues.

Images