Low gate current junction field effect transistor device architecture
Patent Information
- Authority / Receiving Office
- US · United States
- Patent Type
- Applications(United States)
- Current Assignee / Owner
- ANALOG DEVICES INT UNLTD
- Publication Date
- 2019-05-02
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Abstract
Description
FIELD OF DISCLOSURE
[0001] The present disclosure relates to an improved architecture for junction field effect transistors, JFETs, which reduces excess gate current of a JFET, such that the gate current substantially matches the reverse bias diode current that would be expected from the reverse current flow of a reverse biased p-n junction.BACKGROUND
[0002] Broadly speaking field effect transistors, FETs, modulate the width of a “channel” region of semiconductor in order to vary the magnitude of current flowing between current flow terminals of the device. These terminals are known as a drain and a source of the FET.
[0003] The current is modulated by subjecting the channel region to an electric field which can alter the size of depletion regions with the FET. The electric field is generated by applying a voltage to a “gate” of the FET. The gate region is insulated from the channel. The way in which the isolation is achieved can be used to classify FETs.
[0004] In one class of FET, the gat...