Microprocessor with pipeline control for executing of instruction at a preset future time

Abstract

In the disclosure, the microprocessor resolves the conflicts in decode stage and schedules the instruction to be executed at a future time. The instruction is issued to an execution queue until the scheduled time in the future when it is dispatched to a functional unit for execution. The disclosure uses a counter for the functional unit to track when the resource is available in the future to accept the next instruction. The disclosure also tracks the future N cycles when the register file read and write ports are scheduled to read and write operand data.

Description

BACKGROUNDTechnical Field[0001]The disclosure generally relates to a microprocessor, and more specifically, to a microprocessor having an execution pipeline control that issues instructions ahead of time.Description of Related Art[0002]In microprocessor, instructions are pipelined and executed based on the availability of operand register(s) and functional unit(s) corresponding to the instructions (i.e., conflict). The availability of the operand registers includes data dependency and availability of the read and write ports to the register file. If the operand register or the functional unit is not available, the instruction is stalled or put into a queue (e.g., instruction queue) and check again at later time before issuing to the functional unit. When the corresponding operand register and the corresponding functional unit are available, the conflict instruction is then dispatched to the corresponding functional unit for execution. There are 2 options to resolve the conflict: (1)...

AI Technical Summary

Benefits of technology

[0003]The disclosure keeps track of the time when the resource is available in the future and checks for availability of the operands at that future time in order to dispatch an instruction to an execution queue. The disclosure provides necessary register file read and write ports control so that the instruction in the execution queue can be sent to execution pipeline at that specific time in the future. The disclosure also provides mechanism to optionally track the operand conflict time to advance dispatch of the instruction to execution queue. Data dependency checking is in the future when the operands are

Problems solved by technology

The first option is low performance as the instruction is stuck in decode and blocked all subsequent instructions

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