Feedback-pause-controlled radiofrequency carrier tracking for amplitude-modulated signals with an unstable reference clock
a radiofrequency carrier and unstable reference clock technology, applied in the near field of read/write/interrogation/identification system, near field of rfid, instruments, etc., can solve the problem of pll continuing to track an unstable reference clock reference, unreliable rf carrier for emulated-passive devices, appreciable phase and/or frequency errors
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case 1
[0079]Turning to Case 1, conventional pause signal 211-1 de-asserts asynchronously with respect to any of the other illustrated signals at time 910-1. The de-assertion happens to occur just before a rising edge of PLL_fdbk 207. With the phase detector in normal tracking mode (as the pause signal 211-1 has been de-asserted), this rising edge of PLL_fdbk 207 triggers assertion of phase tracking signal 215b-1. Subsequently, a rising edge of PLL_in 205 is detected, triggering assertion of phase tracking signal 215a-1, which triggers a reset. Essentially the same thing can continue to repeat for each subsequent PLL operating cycle (i.e., at each next set of rising edges). In this case, the timing of de-assertion of the pause signal 211-1 happens to support operation of the phase detector in a manner that, from the first cycle, effectively decrease the phase discrepancy between PLL_fdbk 207 and PLL_in 205 in each cycle and result in a fast settle time.
[0080]In Case 2, conventional pause s...
case 4
[0082 in FIG. 9B represents another FPC operation scenario in which PLL_fdbk 207 is lagging PLL_in 205 by a delay (Td). Similar to Case 3, pausing of the PLL tracking is based on FPC signal 809-4, which effectively waits until a next falling edge of PLL_fdbk 207 before de-asserting at time 910-4. For context, two different timing scenarios are shown for a pause signal 211-4 from which the FPC signal 809-4 may be generated. It can again be seen that, regardless of the timing of the pause signal 211-4, the FPC signal 809-4 de-asserts at a time that results in the phase detector making correct compensation determinations (i.e., to effectively decrease the phase discrepancy between PLL_fdbk 207 and PLL_in 205 from the first cycle).
[0083]FIG. 10 shows an illustrative feedback-pause-controlled phase detector 1000 with time limiting, according to various embodiments. The phase detector 1000 can be an implementation of the phase comparison block 210 of the PLL circuit 200 of FIG. 2A, which ...
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