Dummy Insertion Method

Abstract

An integrated circuit (IC) device according to the present disclosure includes a substrate including a first surface and a second surface opposing the first surface, a redistribution layer disposed over the first surface and including a conductive feature, a passivation structure disposed over the redistribution layer, a metal-insulator-metal (MIM) capacitor embedded in the passivation structure, a dummy MIM feature embedded in the passivation structure and including an opening, a top contact pad over the passivation structure, a contact via extending between the conductive feature and the top contact pad, and a through via extending through the passivation structure and the substrate. The dummy MIM feature is spaced away from the MIM capacitor and the through via extends through the opening of the dummy MIM feature without contacting the dummy MIM feature.

Description

PRIORITY DATA[0001]This application is a divisional application of U.S. patent application Ser. No. 16 / 936,676, filed Jul. 27, 2020, which claims priority to U.S. Provisional Patent Application No. 62 / 907,468 filed on Sep. 27, 2019, entitled “SHDMIM DUMMY INSERTION METHOD IN SOIC” (Attorney Docket No. 2019-2372 / 24061.4049PV01), each of which is hereby incorporated herein by reference in its entirety.BACKGROUND[0002]The semiconductor integrated circuitry (IC) industry has experienced rapid growth. Technological advances in IC design and material have produced generations of ICs where each generation has smaller and more complex circuits than previous generations. During the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.[0003]As the semiconductor device scaling down continues, challeng...

AI Technical Summary

Benefits of technology

The patent text describes a method and system for inserting dummy metal-insulator-metal (MIM) structures in semiconductor devices. The technical effects of this patent include reducing uneven etch loading and nonuniform mechanical strength due to uneven distribution of MIM capacitors, and improving the distribution of dummy MIM structures in isolated regions free of MIM capacitors. The method involves forming a first feature over or on a second feature, and may include embodiments in which the first and second features are formed in direct contact or with additional features between them. The patent also describes a system for manufacturing semiconductor devices that includes a device and method for inserting dummy MIM structures. Overall, the patent provides various methods and systems for improving the fabrication of semiconductor devices.

Problems solved by technology

As the semiconductor device scaling down continues, challenges in fabrication may arise.

Presence of through vias that lack long-range orders poses challenges for even distribution of dummy MIM structures, resulting in less-than-optimal reduction of etch loading and reduced mechanical strength.

Therefore, although existing semiconductor fabrication methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

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