Method and system for efficient testing of digital integrated circuits

Abstract

One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

Description

BACKGROUNDField[0001]This disclosure is generally related to testing of physical systems, such as digital Integrated Circuits (ICs). More specifically, this disclosure is related to a system and method for generating testing vectors that facilitate efficient testing of the physical systems.Related Art[0002]Digital Integrated Circuits (ICs) are ubiquitously present in people's life, from washing machines to spaceships. Advances in the lithography technologies have enabled the feature size of the circuits to decrease continuously, thus facilitating the development of high-density ICs. However, as the feature size decreases, defects (e.g., due to impurities in the substrate, misalignments of masks, trembling during exposure, etc.) in ICs become more common and can lead to the malfunction of the circuits. Testing of the ICs is an important step to ensure the quality of the final product comprising the ICs. The increasing complexity of the ICs also increases the cost for testing. It is e...

AI Technical Summary

Benefits of technology

This patent is about a system and method for generating test vectors for testing physical systems, such as digital circuits, using fault-augmented system blocks. The system obtains a design of the system and generates a design of an equivalence-checking system based on the original system. The design of the equivalence-checking system includes a set of fault-assumable inputs that are coupled to a constraint system to simulate different faults. The system can also generate an extended system with additional fault-augmented system blocks and test vectors to test any arbitrary fault in the system. The technical effect of this patent is to provide an efficient and cost-effective way to test the quality of physical systems.

Problems solved by technology

However, as the feature size decreases, defects (e.g., due to impurities in the substrate, misalignments of masks, trembling during exposure, etc.) in ICs become more common and can lead to the malfunction of the circuits.

The increasing complexity of the ICs also increases the cost for testing.

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