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Method and arrangement for extracting a plurality of clock signals

a clock signal and plurality technology, applied in the field of method and arrangement for extracting a plurality of clock signals, can solve the problems of limiting the accuracy or the number of binary positions in the accumulator to practicable values, and the supply of second clock signals

Inactive Publication Date: 2001-07-10
TELEFON AB LM ERICSSON (PUBL)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

However, error propagation is also avoided if the increment supplied in each case to an accumulator is divisible, so as to be remainder-free, in the numerical range that is representable by the predefined bit width, by the largest common divisor of all the clock-pulse conversion ratios to be implemented.

Problems solved by technology

However, particularly in the case of digital modems having asynchronous sampling, the problem arises that a second clock signal is supplied, namely a clock pulse that is rigidly coupled to the symbol clock pulse, but is not coupled to the supplied first clock signal.
In addition, this further development makes it possible for the predefined values to differ insignificantly from the theoretical values which result from the frequency ratios, so that the accuracy or the number of binary positions in the accumulators can be limited to practicable values.

Method used

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  • Method and arrangement for extracting a plurality of clock signals
  • Method and arrangement for extracting a plurality of clock signals
  • Method and arrangement for extracting a plurality of clock signals

Examples

Experimental program
Comparison scheme
Effect test

example 2

s)

Assumptions:

Given the above assumptions, a nominal decimation factor d.sub.nom is expressed as:

d.sub.nom =SAR / DSR=1.348268708

This yields a nominal value i for the phase increment for generating the double symbol rate DSR of (assumption: b=32 bits):

i.sub.nom =2.sup.b *(d.sub.nom).sup.-1 =0.741691915*2.sup.32 =3 185 542 519, . . .

Given an assumed deviation .epsilon.of .+-.0.5%, increments i.sub.+.epsilon.. and i.sub.-.epsilon., are expressed as:

i.sub.+.epsilon. =i.sub.nom (1+.epsilon.)=0.745400374*2.sup.32 =3 201 470 231, . . .

and:

i.sub.-.epsilon. =i.sub.nom (1-.epsilon.)=0.737983455*2.sup.32 =3 169 614 806, . . .

Resulting finally after quantization to whole numbers is:

i.sub.nom =3 185 542 519

i.sub.+.epsilon. =3 201 470 231

i.sub.-.epsilon. =3 169 614 806

These three values result initially without consideration of a clock-pulse conversion to be implemented with the aid of the virtual-PLL concept that is optimized with respect to outlay.

In a link-coded system, as assumed in this examp...

example 3

s; otherwise like Example 2)

Assumptions:

Given the above assumptions, a nominal decimation factor d.sub.nom is expressed as:

d.sub.nom =SAR / DSR=1.348268708

This yields a nominal value i.sub.nom for the phase increment for generating the double symbol rate DSR of (assumption: b=24 bits):

i.sub.nom =2.sup.b *(d.sub.nom).sup.-1 =0.741691915*2.sup.24 =12 443 525.46

Given an assumed deviation .delta.of .+-.0.5%, increments i.sub.+.epsilon.and i.sub.-.epsilon. are expressed as:

i.sub.+.epsilon. =i.sub.nom (1+.epsilon.)=0.745400374*2.sup.24 =12 505 743.08

and:

i.sub.-.epsilon. =i.sub.nom (1-.epsilon.)=0.737983455*2.sup.24 =12 381 307.83

Resulting finally after quantization to whole numbers is:

i.sub.nom =12 443 525

i.sub.+.epsilon. =12 505 743

i.sub.-.epsilon. =12 381 308

These three values result initially without consideration of a clock-pulse conversion to be implemented with the aid of the virtual-PLL concept that is optimized with respect to outlay.

In a link-coded system, as assumed in this exampl...

example 4

s)

Assumptions:

Given the above assumptions, a nominal decimation factor d.sub.nom is expressed as:

d.sub.nom =SAR / DSR=122.0703125

This yields a nominal value i.sub.nom for the phase increment for generating the double symbol rate DSR of (assumption: b=24 bits):

i.sub.nom =2.sup.b *(d.sub.nom).sup.-1 =0.008192*2.sup.24 =137 438.9535

Given an assumed deviation .epsilon.of .+-.0.5%, the increments i.sub.+.epsilon. and i.sub.-.epsilon. are expressed as:

i.sub.+.epsilon. =i.sub.nom (1+.epsilon.)=0.00823296*2.sup.24 =138 126.1482

and:

i.sub.-.epsilon. =i.sub.nom (1-.epsilon.)=0.00815104*2.sup.24 =136 751.7587

Resulting finally after quantization to whole numbers is:

i.sub.nom =137 439

i.sub.+.epsilon. =138 126

i.sub.-.epsilon. =136 752

These three values result initially without consideration of a clock-pulse conversion to be implemented with the aid of the virtual-PLL concept, optimized with respect to outlay.

In a link-coded system, as assumed in this example, the divisor factors of a PLL result mult...

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Abstract

A method and arrangements for extracting a plurality of clock signals for signal-processing circuits, in particular for a digital modem, from a supplied clock signal, for the clock signals to be extracted to be formed in each case from an output signal of an accumulator of predefined bit width n. The accumulator accumulates in each case an increment in the clock pulse of the supplied clock signal and, in the process, performs a modulo2n operation.

Description

The present invention relates to a method and arrangements for extracting a plurality of clock signals for signal-processing circuits, especially for a digital modem, from a supplied clock signal.BACKGROUND INFORMATIONFor the digital generation and modulation of the carrier in modems, the sampling frequency f.sub.A in relation to the symbol frequency f.sub.s can be implemented in two ways. First of all, a fixed, integral ratio can be selected between the sampling frequency and the symbol frequency, so that the sampling is carried out in synchronous form. In addition, the sampling frequency must satisfy the sampling theorem, i.e. it must be greater than double as large (as a rule four times as large) as the symbol frequency. The synchronous sampling demands a is clock-pulse extraction, which extracts the sampling clock pulse from the symbol clock pulse by frequency division.In the case of asynchronous sampling, the sampling frequency is predetermined independently of the symbol frequ...

Claims

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Application Information

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IPC IPC(8): H03L7/099H03L7/08H04L7/02H04L27/20
CPCH03L7/0994H03L7/0805H03L7/099
Inventor AUER, ERICH
Owner TELEFON AB LM ERICSSON (PUBL)