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Non-volatile read-only memory modifiable by redefinition of a metal or via level

a read-only memory and non-volatile technology, applied in the field of integrated circuits, can solve the problems of inability to adapt known conventional means to be simply modified, complex integrated circuits, and increasing complexity

Inactive Publication Date: 2005-04-12
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

According to an alternative embodiment of the memory element such as described hereabove, the first part of the zigzag is cut by removal of a via and the second part of the zigzag is connected to one of the second and third assemblies by addition of a via, on the same via level, between one of the areas of the second part of the zigzag and the rail of one of the sec

Problems solved by technology

Integrated circuits are increasingly complex and it is often necessary to modify a circuit several times after testing and evaluation by the user.
These two solutions raise problems of manufacturing and use.
However, known conventional means are not adapted to be simply modified upon redefinition of a single metal level or of a single via level.

Method used

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  • Non-volatile read-only memory modifiable by redefinition of a metal or via level
  • Non-volatile read-only memory modifiable by redefinition of a metal or via level
  • Non-volatile read-only memory modifiable by redefinition of a metal or via level

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Embodiment Construction

FIG. 1 is a simplified cross-section view of a primary structure 10 of a memory point according to the present invention. The memory point belongs to an integrated circuit comprising several levels of conductive materials called metal levels (M1 to Mi). Each metal level is separated by an insulating layer. A via level enables performing connections between conductive lines formed on adjacent metal levels. Each via level between two adjacent metal levels Mz and M(z+1) will be designated as “Vz−(z+1)”, z being an integer comprised between 1 and i−1. As an example, six metal levels M1 to M6 and 5 via levels v1-2 to v5-6 are used in the examples of implementation discussed hereafter.

Primary structure 10 comprises first 11, second 12, and third 13 assemblies of interconnected metal areas and vias. The first assembly is formed of 6 metal areas 111 to 116, respectively on metal levels M1 to M6, and of 5 superposed vias 111-2 to 115-6, respectively on via levels v1-2 to v5-6, substantially ...

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Abstract

A memory element in an integrated circuit includes several levels of conductive materials separated by insulating levels, each of which is capable of being crossed by conductive vias of an intercalary via level, and at least two connection rails, including several assemblies of successive interconnected areas and vias, a first assembly being formed of a zigzag running from a first metal level to a last metal level and back to the first metal level between a first end and a second end, each of the other assemblies being connected to one of the connection rails, the first end of the zigzag being connected to an initial assembly among the other assemblies.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention generally relates to integrated circuits, and more specifically to a memory point formed over several metal and via levels that can be reprogrammed by modification of any metal or via level.2. Discussion of the Related ArtIntegrated circuits are increasingly complex and it is often necessary to modify a circuit several times after testing and evaluation by the user. Currently, there can be from three to ten successive versions of the same circuit. From one version to another, the circuit modifications are conventionally performed by redefining the metal connections on a single metal level or a single via level.It is desirable to be able to indicate to which version a given circuit belongs. This can be done by marking the chip or the package. These two solutions raise problems of manufacturing and use. Solutions enabling, by an electric testing, determination of the version, require providing a storage means in...

Claims

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Application Information

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IPC IPC(8): G11C17/08G11C17/10H01L27/10
CPCH01L27/101G11C17/10
Inventor LEBOURG, PHILIPPETESI, DAVIDE
Owner STMICROELECTRONICS SRL