Method for fabricating semiconductor device and semiconductor device

a semiconductor and semiconductor technology, applied in the direction of coatings, transistors, chemical vapor deposition coatings, etc., can solve the problems of inability to achieve excellent electric characteristics of capacitors, inability to reduce the size of memory cells, and uneven thickness of ferroelectric films obtained, etc., to achieve excellent electric characteristics

Inactive Publication Date: 2007-01-23
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0017]In view of the above-described problems, the present invention has been devised. It is therefore an object of the present invention to prevent non-uniformity of the composition of a ferroelectric film in the film thickness direction, thereby providing a semiconductor device having good electric characteristics and a method for fabricating the semiconductor device.

Problems solved by technology

Therefore, with the known method, there is a limitation in terms of how much the size of memory cells can be reduced.
With the known method for fabricating a semiconductor device and the known semiconductor, the composition of an obtained ferroelectric film can not be uniform in the film thickness direction.
If the composition of a ferroelectric film is non-uniform in the film thickness direction, excellent electric characteristics of a capacitor can not be achieved.

Method used

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  • Method for fabricating semiconductor device and semiconductor device
  • Method for fabricating semiconductor device and semiconductor device
  • Method for fabricating semiconductor device and semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0064](First Embodiment)

[0065]Hereinafter, a method for fabricating a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. 1.

[0066]FIG. 1 is a flow chart showing a method for fabricating a semiconductor device according to the first embodiment of the present invention.

[0067]A lamination film of indium oxide, iridium and titanium aluminum nitride is formed on a semiconductor substrate in advance, and then a silicon oxide film is formed over the semiconductor substrate so as to cover the lamination film. Furthermore, a recess portion is formed in the silicon oxide film so that part of a surface of the lamination film is exposed through the recess portion (not shown).

[0068]Next, in Step S11, a lower electrode formed of a platinum (Pt) film is formed along inner surfaces of the recess portion in the silicon oxide film by sputtering. Note that the lower electrode may be formed of a lamination film of platinum (Pt) and irid...

second embodiment

[0095](Second Embodiment)

[0096]Hereinafter, a method for fabricating a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. 6.

[0097]FIG. 6 is a flow chart showing a method for fabricating a semiconductor device of the second embodiment of the present invention.

[0098]A lamination film of indium oxide, iridium and titanium aluminum nitride is formed on a semiconductor substrate in advance, and then a silicon oxide film is formed over the semiconductor substrate so as to cover the lamination film. Furthermore, a recess portion is formed in the silicon oxide film so that part of a surface of the lamination film is exposed through the recess portion (not shown).

[0099]Next, in Step S21, a lower electrode formed of a platinum (Pt) film is formed along inner surfaces of the recess portion in the silicon oxide film by sputtering. Note that the lower electrode may be formed of a lamination film of platinum (Pt) and iridium oxi...

third embodiment

[0125](Third Embodiment)

[0126]Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 11.

[0127]FIG. 11 is a flow chart showing a method for fabricating a semiconductor device according to the third embodiment of the present invention.

[0128]A lamination film of indium oxide, iridium and titanium aluminum nitride is formed on a semiconductor substrate in advance, and then a silicon oxide film is formed over the semiconductor substrate so as to cover the lamination film. Furthermore, a recess portion is formed in the silicon oxide film so that part of a surface of the lamination film is exposed through the recess portion (not shown).

[0129]Next, in Step S31, a lower electrode formed of a platinum (Pt) film is formed along inner surfaces of the recess portion in the silicon oxide film by sputtering. Note that the lower electrode may be formed of a lamination film of platinum (Pt) and iridium oxide (IrOx).

[0130]Next, in Step S32, the lower electro...

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Abstract

As a method for fabricating a semiconductor device, a lower electrode is first formed on a semiconductor substrate and then a first ferroelectric film is formed on the lower electrode by CVD using a first source gas. Thereafter, a second ferroelectric film is formed on the first ferroelectric film by CVD using a second source gas. Subsequently, an upper electrode is formed on the second ferroelectric film. In this method, the concentration of bismuth contained in the first source gas is different from the concentration of bismuth contained in the second source gas.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The disclosure of Japanese Patent Application No. 2003-003071 filed on Jan. 8, 2004 including specification, drawings and claims are incorporated herein by reference in its entity.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor device including a ferroelectric film formed by CVD and a method for fabricating the same.[0003]In recent years, further miniaturization has been demanded in the field of ferroelectric memory. With a known method in which a ferroelectric film is formed by coating, however, a ferroelectric film can be formed only on a flat underlying layer. Therefore, with the known method, there is a limitation in terms of how much the size of memory cells can be reduced. Then, to reduce the size of memory cells, a method in which a ferroelectric film is formed using thermal CVD allowing film formation on an underlying layer having level differences has been proposed.[0004]Hereinafter, a known metho...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L27/108H01L21/00H01L21/8242C23C16/40H01L21/02H01L21/314H01L21/316H01L21/3213
CPCC23C16/409H01L21/31604H01L28/56H01L21/31691H01L28/60H01L21/32136H01L28/40H01L21/02197H01L21/02271H01L21/022
Inventor YANO, HISASHIHAYASHI, SHINICHIRO
Owner PANASONIC CORP
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