Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation

Abstract

A method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for example a lower-quality silicon dioxide to be used to fill the deep trench and a higher quality oxide, in an electrically active region, to be used on an uppermost portion of the deep trench without affecting device performance or increasing a possibility of forming polysilicon stringers.

Description

TECHNICAL FIELD[0001]The present invention relates to semiconductor processing. More specifically, the invention is a fabrication method for deep trench isolation and a resulting integrated circuit structure.BACKGROUND ART[0002]To form a semiconductor device, a multitude of elements are formed on or near a surface layer of a semiconductor substrate and electrically connected with each other through conductive lines. Accordingly, there is need for each element formed in a narrow region on the substrate to be electrically isolated from adjacent elements such that the elements are not electrically influenced by each other. For this, in the semiconductor device, an isolation layer or isolation structure is commonly used.[0003]However, as the degree to which semiconductor devices are integrated continues to increase and a size of the various elements is minimized to reduce a distance between the elements or increase a density of the elements, it becomes increasingly difficult to exclude ...

AI Technical Summary

Benefits of technology

[0008]The present invention is a method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for example a lower-quality silicon dioxide to be used to fill the deep trench and a higher quality oxide, in an electrically active region, to be used on an uppermost portion of the deep trench without either affecting device performance or increasing a possibility of forming polysilicon stringers.

[0010]Notice that the third and fourth silicon dioxide layers may be different types of oxide with third oxide (i.e., the deep trench fill oxide) being of a lower quality than the fourth silicon dioxide layer (i.e., the layer in closest proximity to an active device region). Overall fabrication costs are thereby reduced without sacrificing the electrical performance of the active device. A region of the second silicon nitride layer overlaying the first silicon dioxide layer and the first silicon nitride layer prevents any gaps or vertical steps from forming.

Problems solved by technology

However, as the degree to which semiconductor devices are integrated continues to increase and a size of the various elements is minimized to reduce a distance between the elements or increase a density of the elements, it becomes increasingly difficult to exclude inter-element interference.

Low-cost dielectric films typically have less desirable electrical characteristics (e.g., dielectric breakdown strength or higher shrinkage values) than a high-quality film.

However, due to their increased cost (either in terms of material used for their production and / or processing techniques required for their formation and deposition), high-quality films are unsuitable for filling the deep trench.

Overetching the polysilicon film to eliminate stringers is undesirable since (1) increased costs result from added or prolonged fabrication steps or operations; and (2) required conductive features may also be etched away.

The electrical shorts can produce catastrophic failures in one or more active devices on an integrated circuit (IC) chip, consequently leading to low fabrication yield.

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