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Redundancy-free circuits for zero counters

a technology of zero counters and circuits, applied in the field of data processing systems, can solve the problems of low efficiency of components, no added functionality, and redundancy in zero counters such as those used, and achieve the effects of less or no redundancy, improved efficiency, and improved efficiency

Inactive Publication Date: 2008-12-02
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The solution achieves a significant reduction in redundancy, improving speed and power efficiency while making better use of chip area, resulting in a more efficient zero counter circuit.

Problems solved by technology

Many digital devices have components with redundant features that impart no added functionality, and make the component less efficient.
In particular, redundancy in zero counters (leading zeros or trailing zeros) such as those used in LZA 28 has traditionally been considered unavoidable, and zero counter circuits with high redundancy have been used in generations of microprocessors.
Additionally, redundant devices are generally not testable for stuck faults and, consequently, logic with high redundancy often exhibits low test coverage.
However, analysis of the design indicates it may still have a redundancy rate as high as 6.6%, making this circuitry not only harder to test, but also slower and more power consumptive.

Method used

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  • Redundancy-free circuits for zero counters
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Embodiment Construction

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[0038]The present invention is directed to a zero counter which may be used in various execution units of a microprocessor, such as a floating-point unit, to predict the number of non-significant zeros (leading or trailing) in a result. The decoding method described herein removes the redundancy in the prior art zero counter logic using a novel Karnaugh may for a 4-bit base. The present invention takes advantage of the fact that, for the situation wherein all four of the base inputs (a0, a1, a2, a3) are zero, two of the output bits (q1 and q2) can be indeterminate since they will not be selected by the final multiplexer stage. In other words, when q0 is “1”, the base has four zeros regardless of the values for q1 and q2. A simplified Kamaugh map (and thus simplified circuits) may be used to completely achieve the necessary functionality. The Kamaugh map of Table 2 is similar to the prior art map of Table 1 except for the values of q1 and q2 for all zero inputs.

[0039]

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Abstract

A more efficient method of counting the number of zeros in a 4-bit value generates three output bits (q0, q1 and q2) from four input bits (a0, a1, a2 and a3) according to the logic equations q0=not(a1+a2+a3+a4), q1=not(a0+a1), q2=a1(not a0)+not(a0+a2). These output bits yield the number of non-significant (leading or trailing) zeros in the 4-bit value. The invention may be implemented in a 16-bit zero counter having four 4-bit decoders, but is applicable to any number of zero counters. The output bits from the four 4-bit decoders can be combined to yield a 5-bit count whose most significant bit is a one when all input bits from all four of the 4-bit blocks are zero. A multiplexer stage derives two outputs based on a portion of the decode bits. For wider counters, the output stage uses four AOI21 gates to merge additional decode bits from a next lower 16-bit zero counter.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to data processing systems, and more particularly to a method of counting leading or trailing zeros in an arithmetic logic unit such as an execution unit of a microprocessor.[0003]2. Description of the Related Art[0004]The most important element of a computer system is generally the microprocessor which performs logical and arithmetic operations on different types of numbers, or operands. The simplest operations involve integer operands, which are represented using a fixed-point notation. Non-integers are typically represented according to a floating-point notation. Standard number 754 of the Institute of Electrical and Electronics Engineers (IEEE) sets forth particular formats which are used in most modern computers for floating-point operations. For example, a single-precision floating-point number is represented using a 32-bit (one word) field, and a double-precision floating-p...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F7/00
CPCG06F7/74
Inventor KAPLUN, ALEKSANDRWEN, HUAJUN J.
Owner INT BUSINESS MASCH CORP