Redundancy-free circuits for zero counters
a technology of zero counters and circuits, applied in the field of data processing systems, can solve the problems of low efficiency of components, no added functionality, and redundancy in zero counters such as those used, and achieve the effects of less or no redundancy, improved efficiency, and improved efficiency
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[0038]The present invention is directed to a zero counter which may be used in various execution units of a microprocessor, such as a floating-point unit, to predict the number of non-significant zeros (leading or trailing) in a result. The decoding method described herein removes the redundancy in the prior art zero counter logic using a novel Karnaugh may for a 4-bit base. The present invention takes advantage of the fact that, for the situation wherein all four of the base inputs (a0, a1, a2, a3) are zero, two of the output bits (q1 and q2) can be indeterminate since they will not be selected by the final multiplexer stage. In other words, when q0 is “1”, the base has four zeros regardless of the values for q1 and q2. A simplified Kamaugh map (and thus simplified circuits) may be used to completely achieve the necessary functionality. The Kamaugh map of Table 2 is similar to the prior art map of Table 1 except for the values of q1 and q2 for all zero inputs.
[0039]
TABLE 2a0a1a2a3...
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