High speed analog envelope detector

Abstract

A high speed analog transmission envelope (data-validity) detector for detecting the validity or invalidity of received data by generating (and comparing) first through fourth level-shifted signals based on a pair of differential input signals that are externally applied (received). Each of the first through fourth level-shifted signals has voltage levels different from (e.g., higher than) the differential input signals. After comparing the first through fourth level-shifted signals with each other, the comparison results are used in determining the validity of the differential input signals (data). The analog transmission envelope (data) detector flexibly adapts to variations in common mode voltage, and simplifies the circuit architecture because it does not require an additional reference voltage for determining the validity of received data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application 2004-108790 filed on Dec. 20, 2004, the entire contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to analog front ends for high speed serial communication and more particularly to analog transmission envelope detectors operable at the high frequencies of USB2.0.[0004]2. Description of the Related Art[0005]With increases in operating frequencies of central processing units (CPUs) of personal computers (PCs) on the order of several GHz, there have been proposed various high-frequency interfacing systems. For example, there are peripheral component interconnection (PCI) bus systems and IEEE 1284, as kinds of parallel interfacing schemes. Parallel interfacing schemes offer sufficient bandwidth, but there is a disadvantage of too large a...

AI Technical Summary

Benefits of technology

[0018]A high speed (HS) transmission envelope detector (e.g., for use in an analog front end of a USB2.0 transceiver) according to a preferred embodiment of the invention generates first through fourth level-shifted signals in response to differential input signals (e.g., that are received from an external device), the first through fourth level-shifted signals having voltage levels higher than the differential input signal. After comparing the first through fourth level-shifted signals with each other, the compared result is used in determining the validity of data transmitted in the differential input signals. The transmission envelope detector flexibly adapts to variations of the common mode voltage, and simplifies the circuit architecture, (e.g., because it does not need an additional reference voltage for determining the data validity).

Problems solved by technology

Parallel interfacing schemes offer sufficient bandwidth, but there is a disadvantage of too large a data width which increases the number of wires required and the weight and size of cables.

And, if the number of signal lines increases in small apparatuses such as mobile phones, electro-magnetic interference (EMI) increases as well as degradation of power efficiency.

And, the increased number of signal lines occupies more space for the signal lines, making it difficult to miniaturize the small apparatuses.

However, when using the external reference voltage, it is difficult to deal with common-mode (CM) voltage variation because the reference voltage level is independent and fixed.

And it is complicated to construct the circuit due to additional structures of a first differential amplifier to amplify a difference between a reference voltage and an input signal received from the D+ line, and a second differential amplifier to amplify a difference between the reference voltage and an input signal received from the D− line.

Thus, settling a CM voltage takes a long time, and constructing the circuit is complicated as well.

Images