Arbitration circuit and function processing circuit provided therein

Abstract

In an arbitration circuit in which a shared circuit such as a memory is used exclusively by one of a plurality of functional blocks at a time, an access reservation request is issued from one of the functional blocks, and the access request associated with the access reservation request is reserved. Thereafter, when an access request is issued from another functional block, it is determined which one of the access reservation request and the access request from these functional blocks takes precedence. For example, if the access request from the latter functional block has a low priority level, the access reservation request is selected and the circuit waits for an access request from the functional block which has issued this access reservation request. In this manner, it is possible to avoid cancellation of a once-accepted access request and waiting for a high-priority access request.

Description

[0001]The disclosure of Japanese Patent Application No. 2003-375669 filed on Nov. 5, 2003 including specification, drawings and claims is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to an arbitration circuit for arbitration, in using a shared circuit such as a memory, between functional blocks in a circuit such as a digital circuit in which the shared circuit is used exclusively by one of the functional blocks at a time.[0003]Digital circuits that process various data often use memories so as to temporally store data. If a large number of circuits requiring memories (hereinafter, referred to as functional blocks) are provided, the memories are prepared for the respective functional blocks in some cases. However, to implement the same capacity, in both cases of implementation in LSI and on a board, provision of a smaller number of large-capacity memories is more advantageous than provision of a large number of small-...

AI Technical Summary

Benefits of technology

The present invention introduces a technique of using reservation requests in addition to access requests from functional blocks to efficiently arbitrate multiple access requests without canceling or delaying any requests. The invention also includes an arbitration circuit with a shared circuit that can be used exclusively by one of the functional blocks, and a shared-circuit-use-arbitrating circuit for prioritizing and managing the use requests and reservation requests from the functional blocks. The invention further includes an information holding circuit for holding the use requests and reservation requests, a timer for measuring the period of use requests, and an automatic reservation issuing circuit for periodically using the shared circuit. The invention also includes an arbitration circuit with a shared circuit that can be used exclusively by one of the functional blocks, and a shared-circuit-use-arbitrating circuit for prioritizing and managing the use requests and reservation requests from the functional blocks. The invention further includes a data buffer for storing and outputting data from the shared circuit, and a data buffer for inputting data from the outside. The invention provides a more efficient and effective solution for arbitrating multiple access requests and reducing peak performance requirements with minimal hardware resources.

Problems solved by technology

A large number of semiconductors include function cores which require memories, so that the memories and their peripheral components tend to degrade the performance of a system.

In a system performing real-time processing, the latency might cause serious troubles, and thus careful consideration is needed to prevent the latency from causing serious troubles.

However, if the processing is always performed in this manner, access requests with relatively low priority levels might be left unexecuted for a long time.

The former might cause overhead or degradation in performance, and the latter might cause failure of a system.

This increases costs for LSI and memories.

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