Method and layout of semiconductor device with reduced parasitics

Abstract

An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

Description

TECHNICAL FIELD[0001]This invention relates generally to semiconductor devices, and more particularly to devices with reduced parasitics.BACKGROUND[0002]While semiconductor devices have been used in electronic devices such as computers and cellular phones, semiconductor devices are also increasingly used for high power and high frequency applications such as subscriber cable service transmission and cellular base station transmission. Therefore, one of the goals of the semiconductor industry is to develop semiconductor devices that operate at high frequencies as well as provide adequate power for data transmission applications.[0003]One type of semiconductor device used for high power and high frequency applications is the power metal oxide field effect transistor (MOSFET). Of the various forms of power MOSFETs, the Lateral Double-Diffused Metal Oxide Semiconductor (LDMOS) device is commonly used because of its output power capability and high efficiency. Because of its high perform...

AI Technical Summary

Problems solved by technology

As performance requirements have become more demanding, however, semiconductor device manufacturers must continually improve power transistor device performance.

One limitation to power transistor device performance is parasitic capacitance.

In power transistors, parasitic capacitance is particularly problematic because of the large device structures necessary to source and sink large currents, while avoiding breakdown at high voltages.

Besides limiting device performance through the mere presence of capacitive loading, practical considerations in dealing with parasitic capacitance may also lead to higher resistive parasitics.