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Nonvolatile semiconductor storage device including a plurality of memory strings

a nonvolatile, memory string technology, applied in the direction of semiconductor devices, basic electric elements, electrical appliances, etc., can solve the problems of high cost unrealistic introduction of euv exposure devices, and becoming difficult to realize miniaturization from the viewpoint of cost and techniqu

Inactive Publication Date: 2011-09-06
TOSHIBA MEMORY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The solution enables high integration and stable operation of semiconductor storage devices at a lower cost by reducing wiring resistance through the strategic placement of metal layers, facilitating efficient data storage and retrieval.

Problems solved by technology

In recent years, however, it is becoming difficult to realize the miniaturization from the viewpoint of cost and techniques.
However, the cost of an EUV exposure device is high and it is unrealistic to introduce the EUV exposure device when the cost is considered.
Even if miniaturization is achieved, as long as the drive voltage is not scaled, it is expected that breakdown voltage or the like in elements reaches a physical limit point.
That is, there is the high possibility that operation of the device becomes difficult.
In the conventional technique, however, wiring resistance of the stacked conductive layers is larger than a predetermined value, and adverse influence is exerted on the operation stability of a semiconductor storage device.

Method used

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  • Nonvolatile semiconductor storage device including a plurality of memory strings
  • Nonvolatile semiconductor storage device including a plurality of memory strings
  • Nonvolatile semiconductor storage device including a plurality of memory strings

Examples

Experimental program
Comparison scheme
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first embodiment

Configuration of Nonvolatile Semiconductor Storage Device 100 in First Embodiment

[0039]FIG. 1 is a schematic diagram of a nonvolatile semiconductor storage device 100 as a first embodiment of the present invention. As shown in FIG. 1, the nonvolatile semiconductor storage device 100 of the first embodiment mainly has a memory transistor region 12, a word line drive circuit 13, a source-side selection gate line (SGS) drive circuit 14, a drain-side selection gate line (SGD) drive circuit 15, and a sense amplifier 16. The memory transistor region 12 has a memory transistor for storing data. The word line drive circuit 13 controls voltage to be applied to word lines WL. The source-side selection gate line (SGS) drive circuit 14 controls voltage to be applied to a source-side selection gate line SGS. The drain-side selection gate line (SGD) drive circuit 15 controls voltage to be applied to a drain-side selection gate line (SGD). The sense amplifier 16 senses current (or potential) in th...

second embodiment

Concrete Configuration of Nonvolatile Semiconductor Storage Device in Second Embodiment

[0118]A concrete configuration of a nonvolatile semiconductor storage device as a second embodiment of the invention will be described with reference to FIG. 23. In the second embodiment, the same reference numerals are designated to components similar to those of the first embodiment, and their description will not be repeated.

[0119]As shown in FIG. 23, the nonvolatile semiconductor storage device of the second embodiment has, in the memory transistor region 12, a source-side selection transistor layer 20a and a drain-side selection transistor layer 40a which are different from those of the first embodiment. The nonvolatile semiconductor storage device of the second embodiment has, in the periphery region Ph, a peripheral transistor layer 70a different from that of the first embodiment.

[0120]The drain-side selection transistor layer 40a has a drain-side metal layer 43a in place of the drain-side ...

third embodiment

Concrete Configuration of Nonvolatile Semiconductor Storage Device in Third Embodiment

[0125]A concrete configuration of a nonvolatile semiconductor storage device as a third embodiment of the invention will be described with reference to FIG. 24. In the third embodiment, the same reference numerals are designated to components similar to those of the first embodiment, and their description will not be repeated.

[0126]As shown in FIG. 24, the nonvolatile semiconductor storage device of the third embodiment has, in the memory transistor region 12, the source-side selection transistor layer 20, the memory transistor layer 30, a drain-side selection transistor layer 40a, and the wiring layer 50 which are sequentially stacked on the semiconductor substrate Ba. The nonvolatile semiconductor storage device of the third embodiment has, in the periphery region Ph, the peripheral transistor layer 70. That is, the nonvolatile semiconductor storage device of the third embodiment has the characte...

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PUM

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Abstract

A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-43530, filed on Feb. 25, 2008, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to an electrically rewritable nonvolatile semiconductor storage device and a method of manufacturing the same.[0004]2. Description of the Related Art[0005]Conventionally, an LSI is formed by integrating elements in a two-dimensional plane on a silicon substrate. To increase storage capacity of a memory, the dimensions of each element have to be decreased (miniaturized). In recent years, however, it is becoming difficult to realize the miniaturization from the viewpoint of cost and techniques. For miniaturization, the technique of photolithography has to be improved. For example, in the present ArF immersion exposure technique, the rule...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L29/792H10B69/00
CPCH01L27/0688H01L27/105H01L27/11578H01L27/11582H10B43/50H10B43/20H10B43/27
Inventor KIDOH, MASARUKITO, MASARUKATSUMATA, RYOTAFUKUZUMI, YOSHIAKITANAKA, HIROYASUISHIDUKI, MEGUMIKOMORI, YOSUKEAOCHI, HIDEAKINITAYAMA, AKIHIROITO, HITOSHIMATSUOKA, YASUYUKI
Owner TOSHIBA MEMORY CORP