Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor layout scanning method and system

a semiconductor and layout technology, applied in the field of semiconductor layout scanning, can solve problems such as inutility or inconvenient scanning

Active Publication Date: 2013-02-26
APPLIED MATERIALS INC
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011]The scanning mechanism according to the invention scans the objects of the layout. The objects may be polygons or paths. The scanning mechanism identifies, in a two dimensional environment, proximity relations between neighboring object edges and between neighboring corners. Where a proximity relation is found, the corresponding edges or corners are neighbors. The proximity relations are found by searching for edges that have a locally closest point pair in common. Locally closest point pairs show where the interaction between two objects or edges is the most significant. The interaction is the most significant in the places where edges are close together and no other objects are in between. The stored proximities, together with the corresponding edges and corners, are determined by the layout configuration or topology of the semiconductor design layout. The database provides excellent opportunities for layout analysis. The stored proximity information also enables fast search and look up of locations in the layout where a modification is possible or required. Because proximity relations are only identified between direct neighbors, the number of relations is kept relatively small and linear with the number of objects. The proximity based layout compaction or design modification that may be performed after the scanning takes far less computational power than the known methods of the prior art. The method for scanning a semiconductor layout according to the invention is suitable for use in a method for designing and / or producing integrated circuits.
[0019]As long as the topology (which object is left of which other object, which one is below, etc.) of the layout is not altered, the proximity relations provide sufficient information about the semiconductor design layout. If the proximity information is only used for layout analysis no additional information is needed. The topology of the layout changes when the application executes some layout changing actions. A trigger defines a limit for a layout change beyond which limit the corresponding proximity becomes invalid and the topology is changed. The trigger is derived on basis of the stored proximities and the relative positions of the corresponding edges and corners. The trigger may be used for preventing topology changes and for defining the limits within which the topology remains valid.

Problems solved by technology

Depending on the operations to be performed with the proximity information, these additional proximity relations may, or may not be useful.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor layout scanning method and system
  • Semiconductor layout scanning method and system
  • Semiconductor layout scanning method and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0039]FIG. 1 shows a proximity relation 14 between parallel edges of two polygons 11, 12. The polygons 11, 12 represent an area on the semiconductor layout with a particular material, structure or functional element. The two polygons 11, 12 have parallel edges, facing each other. A convex bounding area 13 is drawn, comprising the parallel parts of the edges. A proximity relation 14 between the two polygons is identified, because the convex bounding area 13 is empty, i.e. does not contain any other corner or edge. This proximity relation 14 represents the space between the two neighboring polygons 11, 12. In this example and in the examples following hereinafter, the convex bounding area 13 is a rectangle comprising at least parts of the edges or corners involved in the proximity relation 14. It is however to be noted that, depending of the application, other shapes may be equally or more appropriate for the convex bounding area. The convex bounding area may, for example, be triangul...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method for scanning a semiconductor layout, the layout comprising objects with edges and corners, the method comprising identifying locally closest point pairs, identifying a proximity relation between two parallel edges where the parallel edges have at least one locally closest point pair in common and storing the proximity relation in a proximity relations table of a database together with a reference to the corresponding pair of edges. Locally closest point pairs are identified where the first edge and the second edge are not in contact with each other, a distance between the first point and the second point is the shortest distance between the first edge and the second edge, and a convex bounding area with the first point and the second point on its boundary contains no edge.

Description

[0001]This application is the U.S. national phase of International Application No. PCT / EP2008 / 053302 filed 19 Mar. 2008, which designated the U.S. and claims priority to EP Application No. 07104863.1 filed 26 Mar. 2007, the entire contents of each of which are herebyTECHNICAL FIELD OF THE INVENTION[0002]The invention relates to a method for scanning a semiconductor layout, the layout comprising objects with edges and corners.[0003]The invention further relates to a computer program product and a system for scanning a semiconductor layout and to a method for producing an integrated circuit.BACKGROUND OF THE INVENTION[0004]Scanning of semiconductor layouts is used in layout processing or modification systems that migrate a layout to another technology, systems that make the layout smaller or systems that try to fix violations of constraints in these layouts. A layout migration system tries to calculate a new layout, based on an input layout, such that the new layout fulfills the desig...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(United States)
IPC IPC(8): G06F17/50
CPCG06F17/5081G06F30/398
Inventor EL YAHYAOUI, FARIDVAN GISBERGEN, JOZEFUS GODEFRIDUS GERARDUS PANCRATIUSWILLEKENS, JEROEN PIETER FRANK
Owner APPLIED MATERIALS INC