Partial response trellis decoder for high definition television (HDTV) system

a high-definition television and trellis technology, applied in the field of partial response trellis decoder, can solve problems such as interference and complicated construction of the transmission and reception apparatus of the hdtv

Inactive Publication Date: 2000-12-05
LG ELECTRONICS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The partial response Trellis decoder for a high definition television (HDTV) according to another embodiment comprises: a distance mapper for calculating first, second, third and fourth Euclidean distances between the from input signal and a reference value; a Viterbi decoder for Viterbi decoding the first, second, third and fourth Euclidean distances calculated by the distance mapper; a first delay means for delaying and outputting the Viterbi decoded data for each Euclidean distance; a ruler selector for selecting a ruler type signal based on the signals output by the first delay means; a ha...

Problems solved by technology

In general, if the channel of a NTSC broadcasting station is located in an area adjacent to a HDTV broadcasting station, interference occurs.
However, since the conventional transmission and reception ...

Method used

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  • Partial response trellis decoder for high definition television (HDTV) system
  • Partial response trellis decoder for high definition television (HDTV) system
  • Partial response trellis decoder for high definition television (HDTV) system

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Embodiment Construction

As shown in FIG. 5, a general Trellis encoder includes a precoder 33 for precoding the most significant bit output by a data interleaver, a switch SW.sub.1 for selecting the most significant bit output by the data interleaver if there is no NTSC interference and otherwise selecting the precoded signal output by the precoder 33, a convolutional encoder 36 for convolutionally encoding the least significant bit output by the data interleaver and outputting the same as two bits, and a TCM mapper 37 for receiving a signal consisting of the bit output by the switch SW.sub.1 and the two bits output by the convolutional encoder 36 and for outputting a corresponding voltage level. The general Trellis encoder outputs the most significant bit output by the data interleaver to the TCM mapper 37 without encoding upon receiving the two bit signal output by the data interleaver, and transforms the least significant bit into a two bit signal via the convolutional encoder 36 for output to the TCM ma...

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Abstract

A partial response Trellis decoder that performs Trellis coded modulation in a high definition television (HDTV) having a specific and detailed configuration and includes a distance mapper for calculating first, second, third and fourth Euclidean distances between the input signal and a reference value; a Viterbi decoder for Viterbi decoding the first, second, third and fourth Euclidean distances calculated by the distance mapper; a first delay for delaying and outputting the Yiterbi decoded data for each Euclidean distance; a ruler selector for selecting a ruler type signal based on the signals output by the first delay; and a slicer for slicing the selected ruler type signal and the input signal.

Description

FIELD OF THE INVENTIONThe present invention relates to a partial response trellis decoder for performing trellis coded modulation in a high definition television (HDTV).DISCUSSION OF THE RELATED ARTIn general, a HDTV broadcasting method performs a transmission at the same frequency as that of the National Television System Committee (NTSC), 6 MHz. However, unlike the NTSC, the HDTV broadcasting transmission is performed digitally, allowing for a higher definition when broadcasting and receiving, in relation to the width and length of the screen.The Grand Alliance of the U.S.A. has recently proposed the eight vestigial sideband modulation (VSB) method as a HDTV transmission method. In the 8 VSB method, a symbol composed of two bits is coded into three bits and is then transmitted at eight levels. According to the eight VSB method, after the 2 bit input data is received, the upper bit is not coded in a Trellis encoder but the remaining lower bit is half convolutionally coded to form t...

Claims

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Application Information

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IPC IPC(8): H04L1/00H04L25/497
CPCH04L1/0054H04L25/497H04L1/0065H04L1/0057
Inventor KIM, DAE J.KWAK, HEUNG S.NAM, HO J.
Owner LG ELECTRONICS INC
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