Method for reducing wafer arcing

Abstract

A method for reducing wafer damage during an etching process is provided. In one of many embodiments, the method includes assigning a bias voltage to each of the at least one etch processes, and generating the assigned bias voltages prior to initiation of one of the at least one etch processes. The method also includes applying the assigned bias voltage to the wafer chuck prior to initiation of one of the at least one etch processes. The assigned bias levels reduce wafer arcing.

Description

technical field [0001] The present invention relates to wafer processing methods, and more particularly, to efficient and cost-effective wafer etching operations. Background technique [0002] Modern microchip designs have trended towards more complex chip structures and towards increasing the number of processing steps for a single chip. In particular, the number of interconnect metal layers stacked on top of each other has continued to exceed in the past. Thus, the number of plasma processing steps and the amount of thermostatic intensity induced per wafer during its processing is also increased. As a result of this increased chip fabrication complexity, plasma-induced damage can occur more frequently, leading to device damage and, therefore, resulting in reduced yield of finished wafers. [0003] In typical wafer etching operations, the wafer is held by an electrostatic chuck (ESC) so that the wafer does not move during the wafer etching operation. Under prior art oper...

AI Technical Summary

Problems solved by technology

Therefore, the substrate potential cannot be adjusted in time in response to the increase in the surface potential

Consequently, wafer arcing as described with reference to FIG. 1A occurs, thereby damaging the wafer and reducing wafer yield and profitability.

Images