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Devices and operation methods for reducing second bit effect in memory device

A storage device, bit line technology, applied in electrical components, information storage, static memory, etc., can solve the problems of reducing the storage operation window, lowering, raising and so on

Inactive Publication Date: 2009-04-08
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, the threshold voltage associated with the first bit increases due to increasing the threshold voltage of the second bit, thereby reducing the storage operating window
[0008] The second bit effect reduces the storage operation window for 2 bits / cell operation and / or multi-level cell (MLC) operation

Method used

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  • Devices and operation methods for reducing second bit effect in memory device
  • Devices and operation methods for reducing second bit effect in memory device
  • Devices and operation methods for reducing second bit effect in memory device

Examples

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Embodiment Construction

[0082] Reference will now be made in detail to exemplary embodiments consistent with the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Although the description includes exemplary embodiments, other embodiments are possible, and changes may be made to the described embodiments without departing from the spirit and scope of the invention. The following detailed description does not limit the invention. Rather, the scope of the invention is defined by the appended claims and their equivalents.

[0083] Consistent with the present invention, a semiconductor storage device is provided, which has a source region, a drain region and an AND gate, and a multi-layer structure is formed under the gate. The multilayer structure includes polysilicon layers sandwiched between silicon oxide layers. In one embodiment, appropriate bias v...

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Abstract

A method for operating a semiconductor memory device having first and second bit lines, a gate electrode, an insulative layer, and a substrate includes applying first, second, and third biases to the first bit line, the second bit line, and the gate electrode, respectively, to induce carriers from the gate electrode to the insulative layer, where the carriers have the same type of conductivity as majority carriers in the substrate to thereby reduce a threshold voltage of the semiconductor memory device.

Description

technical field [0001] The present invention relates to methods and apparatus for reducing second bit effects in a memory cell device. Background technique [0002] A flash memory device is a non-volatile semiconductor storage device that retains its stored content even if power is lost. Flash memory devices offer fast read times and offer better shock resistance than hard disks. Accordingly, flash memory devices are common for applications such as memory in battery-powered devices and are widely used in consumer electronics. [0003] In some flash memory devices, one bit of information is stored in each storage unit. More recently, flash memory devices have been developed to store more than one bit per cell. Such devices are often referred to as "multi-level cell" devices. Such multi-level cell devices, such as nitride non-volatile charge-trapping memories, include nitride storage materials. [0004] A single non-volatile charge trapping memory cell typically includes ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/792H01L27/115H01L21/336H01L21/8247G11C16/02H10B69/00
CPCH01L29/7923H01L29/4234G11C16/0475G11C16/0483
Inventor 徐子轩吴昭谊赖二琨
Owner MACRONIX INT CO LTD