Semiconductor structure and method of forming the same

Abstract

A semiconductor structure comprising a plurality of wires formed in an interlayer dielectric (ILD) layer, and a non-planar cap layer formed over the ILD layer and the wires, wherein the cap layer is relative to the wires at locations between the wires raise.

Description

technical field [0001] The present invention generally relates to semiconductor device processing techniques, and more particularly, to a structure for reducing lateral fringe capacitance of a semiconductor and a method of forming the same. Background technique [0002] The continuing trend in the semiconductor industry to form more and more circuit devices within a given area has resulted in significant improvements in the performance of individual integrated circuits and electronic devices incorporating integrated circuits. In a typical integrated circuit, individual integrated circuit components or groups of components are generally electrically connected to each other by a metallization process in which layers of metal are deposited and patterned to form the metal lines that complete the circuit as designed. The individual metal lines formed within the patterned metal layer are isolated from each other by a layer called an interlayer dielectric. These interlayer dielect...

AI Technical Summary

Problems solved by technology

Although the capacitance due to the ILD material 102 can be reduced by replacing silicon dioxide with a lower-k dielectric, it is much more difficult to simply replace the NBLoK cap layer because this layer performs a large number of functions, making it difficult to use a material to replace

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