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Method for improving first-in first-out FIFO performance and first-in first-out FIFO circuit

A first-in-first-out circuit technology, applied in electrical digital data processing, data conversion, instruments, etc., can solve problems such as increased circuit area and time delay, increased drive capability, and increased complexity of address decoders, achieving The effect of saving circuit area and reducing delay

Inactive Publication Date: 2009-07-01
WUXI ZGMICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With the increase of FIFO depth, the complexity of the address decoder also increases, and the required driving capability will also increase, so the circuit area and delay have increased a lot

Method used

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  • Method for improving first-in first-out FIFO performance and first-in first-out FIFO circuit
  • Method for improving first-in first-out FIFO performance and first-in first-out FIFO circuit
  • Method for improving first-in first-out FIFO performance and first-in first-out FIFO circuit

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Experimental program
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Embodiment Construction

[0042] The first embodiment that the present invention provides is a kind of FIFO circuit, and its working principle is as follows figure 2 shown, including:

[0043] The first selector 4S1 of 4 to 1, the first-level register L1 with a depth of 1DW, the second-level register L2 with a depth of 14DW, the third-level register L3 with a depth of 1DW, and the second selector 4S1 with a 4-to-1 selection;

[0044] The output of the first selector 4S1 corresponds to the input of the first-level register L1, the input of the second-level register L2, and the input of the third-level register L3; the output of the first-level register L1 corresponds to the second-level The input of the register L2; the output of the second register L2 corresponds to the input of the third register L3; the output of the third register L3 corresponds to the input of the second selector 4S1.

[0045] The data transfer relationship between each component is as follows:

[0046] When the third-level regi...

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Abstract

The invention discloses a method and a FIFO circuit for improving the performance of a first-in-first-out FIFO, which realizes data push-in and pop-up by means of a three-level register, because when the second-level or third-level register is idle, the first selector The output data only needs to be pushed into idle registers, so the present invention can not only save the circuit area, but also reduce the time delay of the critical path.

Description

technical field [0001] The invention relates to the fields of communication and computer, in particular to the technology of improving FIFO performance. Background technique [0002] With the increase of chip integration, complexity and functional requirements, in many digital circuit systems, it is necessary to provide clock signals of different frequencies and phases for each functional module and peripheral equipment inside the chip. When transferring data between functional modules in these different clock domains, a FIFO (First In First Out) circuit is required to implement data address decoding and data selection. [0003] Currently common FIFO circuits include address decoders and multiplexers, such as figure 1 As shown, a FIFO circuit is provided, which includes: 4 first selectors of 4 selections; 4 register Cells of 16DW (DoubleWord, double word), respectively Cell0, Cell1, Cell2 and Cell3; 4 16 1-to-1 selector, and 4 4-to-1 second selectors. [0004] When data i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F5/06
Inventor 余娜敏
Owner WUXI ZGMICRO ELECTRONICS CO LTD