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Embedded video playing device based on the dual processor

A video playback, dual-processor technology, applied in the direction of digital video signal modification, TV, pulse modulation TV signal transmission, etc., can solve the capacity limitation, the single-core architecture cannot meet the computational load of codec data processing and code stream transmission and reception processing , The structure is limited and it is difficult to customize and expand, so as to achieve strong performance and is conducive to the reuse of software and hardware resources.

Inactive Publication Date: 2007-08-01
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

The single-core architecture usually cannot meet the computational load of encoding and decoding data processing and code stream sending and receiving processing, and there is a big limitation in capacity
Multi-core single-processor architecture, with strong processing capabilities, but the structure is limited and difficult to customize and expand
The multi-processor architecture has the characteristics of flexible structure and powerful performance, but it needs to solve the problem of communication and coordination between processors

Method used

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  • Embedded video playing device based on the dual processor
  • Embedded video playing device based on the dual processor

Examples

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Embodiment Construction

[0019] As shown in Figure 1, a kind of embedded video playback device based on dual processors is provided with two processors, which are responsible for reading the embedded video code stream from video data source devices such as network video server 110 or local disk 160. Formula processor 120 and the DSP decoding processor 140 that is responsible for decoding and playing the video code stream;

[0020] One end of the embedded processor 120 is connected to the video data source device, and the other end is connected to the DSP decoding processor 140 through the dual-port RAM device 130, and the DSP decoding processor 140 is connected to the display 150;

[0021] As shown in Figure 2, the embedded processor 120 includes a code stream reader 210 and a code stream transmitter 220;

[0022] The dual-port RAM device 130 includes a shared register 230 and a code stream register 280;

[0023] The DSP decoding processor 140 includes a code stream buffer 240 , a decoder 250 and a p...

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Abstract

The disclosed embedded video display device comprises one embedded processor to read in video code flow from a video data resource device, and another DSP decoding processor for decoding and displaying video, wherein it can replace the embedded processor for reading in data from low- to high-end, and replaces DSP processor to realize high code-flow high complex audio / video algorithm. This invention integrates advantages of two processors, and has many choices on processor to support processor combination for different performance request.

Description

technical field [0001] The invention relates to the technical field of digital video processing, in particular to an embedded video playback device based on dual processors. Background technique [0002] With the rapid development of information technology, the rapid popularization of the Internet, and the acceleration of the integration of 3C (computer, communication, consumer electronics), the digital age has come. Digital products with embedded network multimedia system as the technical core have become mainstream products in the digital age. Typical embedded network multimedia system embedded video surveillance system (DVR), IP set-top box (IP-STB), portable media player (PMP) and other products all include embedded video playback system. The embedded video playback system is divided into single-core single-processor architecture, multi-core single-processor architecture and multi-processor architecture according to the architecture. The single-core architecture usuall...

Claims

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Application Information

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IPC IPC(8): H04N7/26H04N7/24H04N19/156H04N19/184H04N19/436
Inventor 陈耀武张亮
Owner ZHEJIANG UNIV
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