Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

System and method for implementing packet combined treatment by multi-core CPU

A technology of joint processing and CPU core, applied in the field of communication, can solve the problem of hardware limitation of interrupt overhead, and achieve the effect of avoiding interrupt overhead, improving flexibility, and realizing throughput and delay.

Active Publication Date: 2007-08-08
XINHUASAN INFORMATION TECH CO LTD
View PDF0 Cites 24 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to provide a system and method for realizing joint processing of messages by a multi-core CPU, so as to solve the problem of interrupt overhead or hardware limitation in the joint processing of messages by a multi-core CPU in the prior art

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • System and method for implementing packet combined treatment by multi-core CPU
  • System and method for implementing packet combined treatment by multi-core CPU
  • System and method for implementing packet combined treatment by multi-core CPU

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] Referring to Fig. 6, embodiment 1 of the method provided by the present invention comprises the following steps:

[0048] Step 1, the message is sent and the CPU core processes the message information;

[0049] In this step, after the message sending CPU completes its own processing of the message, it encapsulates the message information into a preset message structure to ensure that the next CPU core can recognize it, for example:

[0050] struct pkt_message

[0051] {

[0052] ulong * packet;

[0053] ulong * pretreat;

[0054] ulong * parameter;

[0055]}

[0056] Step 2, the message sending CPU core identifies the state of the shared message queue, and correspondingly controls the CPU core as the shared message queue corresponding to the message receiving CPU core;

[0057] Step 3, the message sending CPU core writes the message information processed by the CPU core to the shared message queue;

[0058] Step 4, the message receiving CPU core queries w...

Embodiment 2

[0071] Referring to Fig. 9, for embodiment 2 of the method provided by the present invention, the following steps are included:

[0072] Step 21, the message is sent and the CPU core processes the message information;

[0073] Step 22. The message sending CPU core identifies the length of the shared message queue 1. If it is less than the preset minimum threshold value of 1min, it indicates that no congestion occurs, and executes step 27; it is greater than the preset minimum threshold value of 1min and less than the preset When the maximum threshold value is 1max, perform step 23, and when it is greater than the preset maximum threshold value 1max, perform step 24;

[0074] Step 23, shortening the length of the shared message queue corresponding to the CPU core as the message receiving CPU core, and performing step 27;

[0075] Step 24, indicating that the shared message queue is full, and buffering the processed message information;

[0076] Step 25, identifying the shared...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a multi-core CPU message processing system, including multi-core CPU and a number of shared queues. Every shared queue is connected to two determined CPU cores, serving as shared message queue for the two CPU cores: the sender CPU core of the shared queue writes the message it has processed to the queue, and the receive CPU core gets the message in the same order of write to process. The invention also discloses a combined approach by multi-core CPU where the message sender CPU core write the message it has processed to the shared queues and the receive CPU core gets the message in the same order of write to process. The invention avoids the interruption expenses and it is no longer confined to the CPU hardware space constraints, increasing the flexibility of queue design and throughput.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a system and method for realizing joint processing of messages by multi-core CPUs in communication data processing equipment. Background technique [0002] Since each core of a multi-core CPU can run an independent task, which improves processing throughput and processing efficiency, it is increasingly widely used in communication data processing devices. At present, there are two working modes of the multi-core CPU in the communication data processing equipment, including the pipeline mode and the parallel mode to process the message. For the pipeline method, each CPU core completes part of the message processing, and after the part of the processing is completed, the control of the message is transferred to the next CPU core to continue processing, realizing the joint processing of the message by the multi-core CPU , as shown in Figure 1, a task (Task) is decomposed int...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F9/46H04L12/58
Inventor 郭昕
Owner XINHUASAN INFORMATION TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com