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Embedded system and control method thereof

A control method and embedded technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problems of important and sensitive setting time of different signals, increasing data ratio of serial flash memory, etc., and achieve the effect of increasing accuracy

Active Publication Date: 2007-09-26
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the data rate of serial flash memory is increasing day by day, making the setup time of different signals extremely critical and sensitive

Method used

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  • Embedded system and control method thereof
  • Embedded system and control method thereof
  • Embedded system and control method thereof

Examples

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Embodiment Construction

[0071] A detailed description of the present invention will be provided below. Please refer to Figure 1. FIG. 1 is a first embodiment showing a block diagram of an embedded system 100 provided by the present invention. The embedded system 100 includes an access circuit, which may be a chip (such as an ASIC) 110 and a series of flash memories 120 . The chip 110 can read or write data into the serial flash memory 120 through three input / output pins C, Q, D. Chip 110 includes a processor (eg, CPU) 112 , a plurality of parallel-to-serial shift registers 114 , a serial flash memory controller 116 , and a timing compensator, which may be a phase sampler 118 . The processor 112 controls the overall operation of the chip 110 . The plurality of parallel-to-serial shift registers 114 convert parallel signals into serial signals. The sequence flash memory controller 116 is to activate a spontaneous (free-run) clock signal CLK source To generate an operating clock signal CLK inship ...

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Abstract

The invention relates to an embedded system, and in particular, to an embedded system capable of compensating setup time violation. An embedded system comprises a serial flash and an access circuit. The serial flash further comprises an input pin and an output pin. The access circuit further comprises a processor, a shift register, a serial flash controller, and a time compensator. The input pin receives an adjusted input signal and the output pin sends an output signal. The processor controls the operation of the access circuit. The serial flash controller enables an operational clock of the access circuit. The time compensator compensates a timing of the output signal by referring to the operational clock. The shift register converts data in parallel form to serial form.

Description

technical field [0001] The present invention relates to an embedded system, and more particularly to an embedded system for compensating setup time violations (Setup Time Violation). Background technique [0002] Embedded systems typically include flash memory to store data and program codes, such as serial flash memory (Serial flash) or parallel flash memory (Parallel Flash). An embedded system requires multiple pins (address pins, data pins, and control pins) to access a parallel flash memory. Accessing serial flash memory requires fewer pins. However, the data rate of serial flash memory is increasing day by day, making the setup time of different signals extremely critical and sensitive. Contents of the invention [0003] The main object of the present invention is to provide an embedded system that can be used to compensate for setup time violations. The embedded system includes a series of flash memories and an access circuit. The serial flash memory also include...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
CPCG06F13/4291
Inventor 赖明祥蔡忠宏
Owner MEDIATEK INC
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