Flexible part automatic transition double processor and single processor method

Abstract

This invention relates to one flexible automatic conversion processor and single processor method, which comprises the following steps: establishing multiple HT OEM Table in computer system memory relative to different processor number; when system is started, system first central processor identifies system number and then loads the central processor number into relative HT OEM Table; system according to initial connection between each element finally executing BIOS initial process.

Description

【Technical field】 [0001] The present invention relates to a method for automatic conversion of dual processors and single processors by firmware. When the system is turned on and the input and output elements have not been initialized, it is firstly determined whether the system is a single processor system or a dual processor system. As a result, the appropriate HT OEM Table is loaded and initialized, so that the designer does not need to think too much about whether the system is a single processor or a multi-processor when designing firmware, thereby increasing the convenience of firmware design. 【Background technique】 [0002] As applications become more and more complex, relatively computer systems need more computing power to handle a large number of complex tasks. In order to improve the processing efficiency of the computer system, a multi-processor system is gradually developed from a single processor, so that a task can be executed in parallel through multiple proc...

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Problems solved by technology

[0006] What Fig. 1 depicts is the system architecture diagram of existing multiprocessor, and this system comprises a first central processing unit 10 and a second central processing unit 11, wherein the first central processing unit 10 and the second central processing unit 11 pass the first central processing unit 10 and the second central processing unit 11 The bus 12 is connected to each other, and the first central processing unit is also connected with the second south bridge chip 15 and the first south bridge chip 16 respectively through the second bus 13 and the third bus 14, which is uniformly controlled by the first central processing unit 10. Two central processing units 11, the first south bridge chip 15 and the second south bridge chip 16, so although the dual-processor architecture is used, most of the resources are carried out by the first central processing unit 10, thus the execution efficiency is not good

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