Layout architecture with high-performance and high-density design

Abstract

The present invention relates to a layout structure with high performance and high density design for a standard cell integrated circuit. The layout structure includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first element area, a second element area, a third element area, and a fourth element area. The first element region is disposed on the substrate and adjacent to the first conductor. The second element area is disposed on the substrate, adjacent to the first element area, and below the second conductor. The third element area is disposed on the substrate, adjacent to the second element area, and below the third conductor. The fourth element area is disposed on the substrate and located between the third element area and the fourth conductor.

Description

technical field [0001] The present invention relates to a layout architecture, and more particularly to a layout architecture with high performance and high density design. Background technique [0002] FIG. 1 is a layout diagram of an existing standard cell. The existing standard cells C1-C4 are located between the conductors T1 and T2, and can perform different functions such as amplifiers, adders, multipliers, and inverters, respectively. Therefore, the standard cells C1 to C4 are arranged with different widths W1 to W4 according to the complexity of the functions. In FIG. 1 , the width W4 is greater than the width W2 , so, under the same height H1 , the layout area of ​​the standard cell C4 is larger than that of the standard cell C2 . Therefore, the standard cell C4 is suitable as a layout structure for a circuit with a relatively complex design or a circuit with a large driving current, and the standard cell C2 is suitable for a layout structure for a circuit with a ...

AI Technical Summary

Problems solved by technology

However, the biggest disadvantage of this layout structure is that it is different from the entire area of ​​the P-type MOS region 322. The areas of the N-type MOS regions 321 and 323 are separated. This separation makes some circuits unable to be shared and requires repeated design, which increases the complexity. And it is easy to cause part of the layout area to be wasted

And the connecting wire is too long, which increases the difficulty of winding

Images