Method for using FPGA to process network data packets in optical network

Abstract

The invention provides a method, which uses FPGA distribution to process network data message in the optical fiber network. The invention comprises the following steps: 1. n buffer zones are mounted inside the FPGA, which are instantiated as FIFO. The FIFO is used for storage of the awaiting forwarding network data messages and the related information; 2. The readability of n FIFO is polled, reading operation is carried out on readable FIFO, read data is forwarded to n gigabit exits, each readable FIFO is read for more than two time ticks and is switched to a next FIFO; 3.After one polling and reading operation for n FIFO, the step 2 is repeated. The method of the invention can largely improve the exit bandwidth of a multi-output port, buffer the impact flow of some port, and avoid generation of wrong data message, which is caused by buffer overflowing of some port due to the impact flow.

Description

Technical field: [0001] The invention belongs to the technical field of optical network communication, and in particular relates to a method for processing network data messages by using FPGA in an optical network, which can be applied to access equipment of a 10G optical network. Background technique: [0002] At present, most of the backbone networks in the wired communication field are 10G optical networks. The 10G optical signals must be converted into 1000base signals of multiple lines through hardware access equipment, so that they can be directly connected to PCs or servers through Gigabit Ethernet cards. To analyze and process network data packets. In the hardware access device, the technology based on FPGA design is used to divide and process the network data packets. After the data packets accessed from the 10G optical network enter the FPGA, after some processing, they will finally be sent out from n gigabit exits and connected to the back-end equipment. FPGA is...

AI Technical Summary

Problems solved by technology

[0004] First of all, the data packets that may be accessed from the 10G optical network at a certain moment all have a certain hash value or a certain segment, resulting in a particularly large amount of data on a certain Gigabit port in a certain microscopic period of time, resulting in The ingress bandwidth of 10Gbps and the egress bandwidth of 1Gbps must require a larger buffer inside the FPGA to buffer the "impact traffic"

[0005] Secondly, because the data packet buffer of the Gigabit port chip itself is also limited, if the FPGA reads data packets from each egress buffer and forwards them to the Gigabit port chip according to the efficiency of the full bandwidth, a certain moment will also appear Forwarding with a bandwidth of 10Gbps, but for Gigabit port chips, it can only send externally at a bandwidth of 1Gbps, so it may also cause buffer overflow of the Gigabit port chip and generate error messages, so the internal logic of the FPGA must be able to monitor the peripheral The state of the chip determines whether to forward data packets according to the water level of the buffer of its gigabit port

[0006] Thirdly, since the n Gigabit ports corresponding to data forwarding share a set of data and clock buses, if a complete data message is taken as a unit, the data messages of other Gigabit ports are transmitted after a complete data message is transmitted. The transmission will cause the buffers of other Gigabit ports to be idle, and it will also cause the "tension" of the internal buffer of the FPGA, which will eventually cause the efficiency of the Gigabit ports to be low, and a large number of data packets will be discarded inside the FPGA.

As shown in Figure 1, it is a schematic diagram of a method for processing network data packets by FPGA. This method uses a large buffer to store all outgoing data packets, and then uses a complete The data is forwarded in units of messages; its advantages are single interface, simple logic, and convenient implementation. The disadvantage is that the efficiency is not high, and the buffer inside the gigabit chip cannot be fully utilized; for example, the FPGA must continuously send data messages 1, 2, 3, 4, if the forwarding is based on a complete data message, then when the message 1 is sent until 1 is sent, other gigabit ports will be idle, which reduces the efficiency of gigabit egress

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