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Digital synchronization series simple instrument implementing device

A series of digital technologies, applied in the field of digital synchronous series of simple instrument realization devices, can solve the problems of expensive test instruments, etc., and achieve the effect of improving the one-time pass rate, having more ports, and supporting more services

Inactive Publication Date: 2010-12-08
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, SDH test instruments are very expensive. In order to reduce the cost of instrument use, a simplified SDH test instrument for production and debugging can be developed to meet production needs.

Method used

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  • Digital synchronization series simple instrument implementing device
  • Digital synchronization series simple instrument implementing device
  • Digital synchronization series simple instrument implementing device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0061] Embodiment 1, a simple SDH bit error detector for STM-1 / STM-4 / STM-16 based on the STM-16 multiplexing chip.

[0062] Such as Figure 4 Shown is the implementation block diagram of the first embodiment. In this embodiment 1, based on the STM-16 multiplexing chip, a simple SDH bit error detector with three rates STM-1 / STM-4 / STM-16 is constructed.

[0063] The multiplexing chip of STM-16 can generally complete the multiplexing and demultiplexing of 16 STM-1, or 4 STM-4, or their combination to STM-16. In theory, it can complete the multiplexing and demultiplexing with one STM-16 rate, and 16 STM-1 rate or 4 STM-4 rate ports or a combination of SDH simple instruments, for the sake of simplicity, the simple instrument we define here includes 1 STM-16, 2 channels of STM-4, 2 channels of STM- 1 SDH bit error test function of three rates.

[0064] The block diagrams and structures of the three rates are the same, but the ports of the chips are different, and the supported se...

Embodiment 2

[0083] Embodiment 2, a simple SDH bit error detector based on the STM-16 / STM-64 of the STM-64 multiplexing chip.

[0084] Such as Figure 5 As shown, this embodiment 2 is based on the STM-64 multiplexing chip to construct a simple SDH bit error detector with two rates of STM-16 / STM-64. The STM-64 multiplexing chip can generally complete the multiplexing and demultiplexing of 4 STM-16 to STM-64, and now use the built-in PRBS module to generate data signals from the inside, which can realize 4 STM-16 and 1 STM-64 SDH error code test function.

[0085] exist Figure 5 Among them, the block diagram and structure of the two rates STM-16 and STM-64 are the same, but the ports of the chips are different, and the supported service rates are different. In order to simplify the length of the description, only STM-64 is used as an example to illustrate. The principle of STM-16 is the same as that of STM-64, and relevant descriptions are made at the same time. The block diagram of STM...

Embodiment 3

[0097] Embodiment 3, SDH simple bit error detector based on STM-1 / STM-4 / STM-16 of FPGA high-speed chip.

[0098] Such as Image 6 Shown is the implementation block diagram corresponding to Embodiment 3. In Embodiment 3, an SDH simple bit error detector with three rates STM-1 / STM-4 / STM-16 is built on the basis of FPGA. The scheme of this embodiment 3 is the same as that of the above-mentioned embodiment 1, and the difference is that only the means of realization are different. In the embodiments 1 and 2, a framer (FRAMER) is used to construct it, while in the embodiment 3, an FPGA is used to construct it. In Embodiment 3, the FPGA can flexibly configure the rate of ports, each port can be set as STM-1 / STM-4 / STM-16, and the number of ports can be increased or decreased as required. For the sake of simplicity, it is defined that the simple instrument in Embodiment 3 includes SDH bit error testing functions of three rates: 1 STM-16, 2 STM-4, and 2 STM-1.

[0099] Image 6 The b...

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Abstract

This invention discloses a device for realizing simplified digital synchronous sequence instrument, which applies a current technological platform to realize cost to SDH equipment and test of error codes, at the sending direction, a data sequence generating unit generates data load to form a synchronous transfer mode signal of the synchronous digital sequence STM-N after channel process and segment process to be sent to a being tested unit, at the receiving direction, it receives being tested digital synchronous optical signals from the being tested unit to carry out photoelectric conversion to change it to electric signal to separate data sequence from it by segment and channel process and then a data sequence check unit compares the sequence with the pre-set data generated by the generating unit and presents a system bit error code and carry out error code instruction and report.

Description

technical field [0001] The invention relates to a test device of a digital synchronization system in the field of communication technology, in particular to a digital synchronization series simple instrument realization device for detecting overhead and error codes. Background technique [0002] At present, the mainstream of communication equipment is still digital synchronous series (SDH, Synchronous Digital Hierarchy) equipment, and services such as ATM (Asynchronous Transfer Mode) and GE (Gigabit Ethernet) can be assembled on SDH services for transmission, which can improve transmission efficiency. Reduce the cost per unit of bandwidth. With the increase of demand and the advancement of technology, the transmission rate of SDH is getting higher and higher, from the original STM-1 to the current STM-256. The data multiplexing technology is used to synthesize low-speed SDH services into high-speed SDH services, which improves transmission efficiency, saves optical fiber re...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06H04J3/14
Inventor 武二中
Owner ZTE CORP