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Method for establishing rate of finished products model of memory element circuit using effective area

A technology of circuit yield and effective area, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as unguaranteed yield and waste of chip area

Active Publication Date: 2010-06-09
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If there are too many repair resources, the area of ​​the chip will be wasted. If there are too few repair resources, the final yield cannot be guaranteed.

Method used

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  • Method for establishing rate of finished products model of memory element circuit using effective area
  • Method for establishing rate of finished products model of memory element circuit using effective area
  • Method for establishing rate of finished products model of memory element circuit using effective area

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0031] Now with the typical data join figure 1 The program flow illustrates the concrete process of the inventive method:

[0032] 1. Establishment of memory raw yield model

[0033] The original yield model of the memory circuit is established based on the effective area of ​​the power-off and leakage defects of each layer or each process module and the number of single contact holes. The yield model includes the yield of each layer or each process module and the yield of each contact hole, and their product is the final initial yield of the entire memory product.

[0034] The following uses the SRAM memory unit as an example to illustrate this process. Generally speaking, a SRAM memory cell contains AA, POLY, CONTACT, M1, VIA1, M2, VIA2 and M3 layers. The surrounding circuit may contain other high-level metals such as M4 and M5 and contact hole VIA4. Its raw yield is composed of the power-off and leakage yield of each layer and the yield of each contact hole. Therefore,...

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PUM

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Abstract

The invention relates to a method of using effective area to establish a memory circuit yield model, and comprises: (1) establishing the memory primary yield model; (2) establishing a memory characteristic failure yield model; (3) the repairing and calculating of the memory characteristic failure; (4) the calculating of final yield of the memory; (5) the reciprocal calculating for the memory characteristic failure and the rate of defect of a process model, and establishing the memory circuit yield model. The method of the invention can exactly forecast the primary yield, the yield after repairing, and the main failure characteristic yield by using a design map of the memory, an available repairing resource of the memory and a defect rate curve of each process model of a production line, furthermore, the invention can optimize the design of repairing resource.

Description

technical field [0001] The invention relates to the field of integrated circuit design and manufacture, in particular to a method for establishing a yield model of a memory circuit using the concept of effective area. Background technique [0002] Traditionally, the estimation of memory yield is obtained by comparing it with logic circuits. Such a method is not very accurate because it does not take into account the particularity of the memory circuit. Establishing an accurate yield model has very good guiding significance for the design and manufacture of memory circuits. For example, when designing a new memory circuit, its final yield is very important. In order to ensure an appropriate yield, it is necessary to pre-design repair resources. If there are too many repair resources, the area of ​​the chip will be wasted. If there are too few repair resources, the final yield cannot be guaranteed. If an accurate yield model can be established, the design of repair resourc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 任杰郑勇军马铁中史峥严晓浪
Owner ZHEJIANG UNIV