Automatic testing device and method for multi-JTAG chain

Abstract

The invention discloses an automatic test device used for multi-JTAG chain and a method. The device comprises a control module used for accomplishing the read-write operation of the network element data of at least one veneer at one time according to the state diagnosis command from an external access device and returning the result to the external access device, a connection module used for connecting at least one veneer in series into a daisy chain and providing the input data signal line of a first channel of the veneer and the output signal line of a last channel of the veneer to the control module and connecting the JTAG control line and the clock line of the control module in parallel to at least one veneer. The invention can accomplish the read-write operation of the local / remote network element data of all the chips on all the single boards at one time.

Description

technical field [0001] The invention relates to the communication field, in particular to an automatic test device and method for multiple JTAG chains. Background technique [0002] In the current electronic communication system, especially in the network element communication equipment composed of multiple single boards with complex functions, each single board generally adopts multiple highly integrated chips such as MPU (processor), FPGA (field programmable Logic array), CPLD / EPLD (programmable logic device), these chips basically provide a separate JTAG diagnostic interface. By using the JTAG diagnostic interface, the state of the internal register of the chip can be read, thereby realizing the state diagnosis of the chip. [0003] However, in the actual application environment, a system is often composed of dozens to hundreds of communication network elements, and each network element is composed of more than a dozen boards, and each board consists of about 4 to 6 chips...

AI Technical Summary

Problems solved by technology

Therefore, when diagnosing a fault, although a single read and write operation can be performed on the internal registers of individual chips on the board, the operation is complicated and inefficient, and, after the MPU runs dead, no register value can be read

At present, inside the network element equipment, there is no connection between the boards, or even the JTAG interface inside the single board, and the network element equipment has no corresponding external interface, so it is impossible to realize the automatic test of the system equipment using the JTAG interface

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