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Exposure mask and method for fabricating semiconductor device using the same

A semiconductor and mask technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, and components used for optomechanical processing, etc., can solve problems such as device failure and damage

Inactive Publication Date: 2008-06-25
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the recessed region 16 is formed, the edge of the adjacent active region 14 is damaged at location "A", which can lead to device failure

Method used

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  • Exposure mask and method for fabricating semiconductor device using the same
  • Exposure mask and method for fabricating semiconductor device using the same
  • Exposure mask and method for fabricating semiconductor device using the same

Examples

Experimental program
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Effect test

Embodiment Construction

[0016] image 3 is a layout diagram showing an exposure mask according to an embodiment of the present invention. A device isolation structure 22 is formed in the semiconductor substrate 20 to define an active region 24 . A portion of the active region 24 is etched away by a photolithography process using a wave-shaped mask pattern (not shown) to form a recessed gate region 26 . In the recessed gate region 26 , the critical dimension of the portion near the edge of the active region 24 is 4 nm smaller than that of the rest of the recessed gate region 26 . A gate oxide film (not shown) is formed over semiconductor substrate 20 in active region 24 and recessed gate region 26 . A gate polysilicon layer (not shown), a tungsten layer (not shown) and a gate hard mask layer (not shown) are sequentially formed over the semiconductor substrate 20 and in the recessed gate region 26 . The gate hard mask layer, the tungsten layer and the gate polysilicon layer are patterned by a photoli...

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PUM

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Abstract

An exposure mask for recess gate includes a transparent substrate and a recess gate pattern. The recess gate pattern is disposed over the transparent substrate. The recess gate pattern includes a first portion having a first line width and a second portion having a second line width smaller than the first line width. In the second portion, elements of the recess gate pattern are separated.

Description

technical field [0001] The present invention generally relates to methods of fabricating semiconductor devices. More particularly, the present invention relates to a method of manufacturing a semiconductor device using an exposure mask. Background technique [0002] As the design specifications of semiconductor devices are significantly reduced, the gate resistance value of cell transistors is increased. Therefore, planar transistor structures have limitations in terms of gate resistance and threshold voltage. Methods have been developed to ensure channel length without increasing design specifications. In order to extend the channel length while maintaining a small critical dimension (CD) of the gate, a recessed channel structure has been studied. In the recessed channel structure, the semiconductor substrate is recessed, and the gate is formed above the recessed semiconductor substrate to extend the effective channel length. [0003] 1 and 2 are views illustrating a re...

Claims

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Application Information

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IPC IPC(8): G03F1/14G03F1/00G03F7/00H01L21/027
CPCH01L21/3083G03F1/14H01L29/66621H01L21/28123G03F1/00G03F1/62H01L21/0274
Inventor 郑龙淳
Owner SK HYNIX INC
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