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A measurement construction to enhance the electricity thickness measuring stability of an oxide layer of P trap bar

A technology of electrical thickness and gate oxide layer, which is applied in the direction of circuits, electrical components, and electrical solid-state devices, can solve the problems of large fluctuations in the electrical thickness of the P-well gate oxide layer, improve measurement stability, reduce re-measurement, The effect of saving production cost

Active Publication Date: 2008-07-09
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
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Problems solved by technology

[0005] Since the P well 1' and the P-type substrate 2' in the measurement structure are automatically and directly connected together, during the test, the entire 8-inch silicon wafer is a P-type substrate, and is directly It is placed on the test machine, so when the test machine is unstable, it often occurs that the noise signal of the P-type substrate is induced into the test signal, so the P-well gate oxide layer measured using the above measurement structure The electrical thickness Tox fluctuates greatly

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  • A measurement construction to enhance the electricity thickness measuring stability of an oxide layer of P trap bar

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[0019] As shown in Figure 2, the measurement structure for improving the stability of the electrical thickness measurement of the P-well gate oxide layer provided by the present invention includes a P-well 1, a P-type substrate 2, and a substrate lead-out terminal B 3 and a gate electrode G The terminal 4 is characterized in that it also includes a deep N well structure surrounding the two sides and the bottom of the P well 1;

[0020] The gate electrode G terminal 4 is respectively arranged on the upper end of the P well 1 and the upper end of the P-type substrate 2, and is connected by a wire to form a measurement terminal;

[0021] The deep N well structure includes a deep N well layer 9 and an N well layer 10; the deep N well layer 9 is arranged at the bottom of the P well 1, and the N well layer 10 is respectively arranged on both sides of the P well 1, and the P Surrounded by the well 1, the P well 1 is completely isolated from the P-type substrate 2;

[0022] The P-typ...

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Abstract

The invention relates to a measurement structure which can improve the measurement stability of the electrical thickness of a P-well grid oxide layer, comprising a P-well, a P-typed substrate, a substrate leading-out pole B end and a grid electrode G end; the invention further comprises a deep N-well structure which surrounds at the two sides and the bottom part of the P-well; the grid electrode G end is respectively arranged at the upper end of the P-well and the upper end of the P-typed substrate, a measurement end is constituted by the connection of the leading wires; the deep N-well structure comprises a deep N-well layer which is arranged at the bottom part of the P-well and N-well layers which are respectively arranged at the two sides of the P-well; the P-typed substrate surrounds at the two sides and the bottom part of the deep N-well structure. The measurement structure which can improve the measurement stability of the electrical thickness of the P-well grid oxide layer that is provided by the invention makes use of the deep N-well technology in RFCMOS and HV processes, thus the invention can greatly improve the measurement stability of the electrical thickness of the P-well grid oxide layer and reduce the occurrence of the situations that a re-measurement is needed because measurement results exceed specifications, or a product is scrapped caused by instable measurement.

Description

technical field [0001] The invention relates to a measurement structure for measuring the electrical thickness of a gate oxide layer in a semiconductor process, in particular to a method for improving the gate oxidation of a P well by using the deep N well process in the RFCMOS (Radio Frequency Complementary Metal Oxide Semiconductor) and HV (High Voltage) process. Measuring structure for layer electrical thickness Tox measurement stability. Background technique [0002] In the semiconductor process, the measurement of the electrical thickness Tox of the gate oxide layer is one of the most important test items. But at present, in the actual WAT (Wafer Acceptance Test, Wafer Acceptance Test) measurement process, it is often found that the measurement results of the electrical thickness Tox of the P-well gate oxide layer fluctuate greatly, and it often happens that the measurement results exceed the specifications and must be In the case of re-measurement, this will cause hug...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544
Inventor 黎坡胡剑
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP