Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. According to some embodiments, a semiconductor device comprises a lower structure formed on a semiconductor structure. The lower structure has chip pads. The semiconductor device further comprises a passivation layer located over the chip pads. The passivation layer comprises first openings defined therein to expose at least a portion of the chip pads. The semiconductor device additionally includes at least two adjacent redistribution lines spaced apart from each other and located over the passivation layer. The at least two redistribution lines are respectively coupled to the chip pads through corresponding ones of the first openings. The semiconductor device comprises a first insulation layer located over the passivation layer. The first insulation layer includes a void extending between the at least two adjacent redistribution lines.

Description

[0001] This application claims the benefit of Korean Patent Application No. 2007-0010377, filed February 1, 2007, and U.S. Patent Application No. 12 / 016.677, filed January 18, 2008, the contents of which are entirely incorporated by reference in this. technical field [0002] Embodiments of the present invention generally relate to a semiconductor device and a manufacturing method. More particularly, some embodiments of the present invention relate to a semiconductor device including redistribution lines and a method of manufacturing the same, wherein the semiconductor device is adapted to reduce parasitic capacitance between adjacent redistribution lines. Background technique [0003] In the manufacturing process of modern semiconductor devices, it is often required that the bonding pads of semiconductor chips assembled in different package types are rearranged to suit the different package types. However, changing the overall distribution of electrical components of a sem...

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Problems solved by technology

[0010] However, as the level of integration inside a semiconductor chip increases, the distance between adjacent redistribution lines is greatly reduced

As a result, the parasitic capacitance generated between adjacent redistribution lines increases undesirably, which will cause significant signal delay and greater power consumption

In addition, it is already known in the art that such parasitic capacitance in various semiconductor devices such as flash memory causes signal interference, thereby reducing the reliability of the resulting electronic products

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