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Multi- core processor efficiency regulation method

An adjustment method and a processor technology, applied to architectures with multiple processing units, data processing power supplies, general-purpose stored program computers, etc., can solve the limitation of improving the overall performance of multi-core processors and cannot perform well in single-core processors. Multitasking advantages and more

Active Publication Date: 2008-08-13
ASUSTEK COMPUTER INC
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  • Application Information

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Problems solved by technology

[0010] Therefore, although these processing cores theoretically have multiple times the computing power of a single processor, when the computing bottleneck is concentrated on a single processing core, the improvement of the overall performance of the multi-core processor is still limited and cannot perform as expected. Multitasking advantage over single-core processors in

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Embodiment Construction

[0022] FIG. 1 is a block diagram of a multi-core processor system according to an embodiment of the present invention. This multi-core processor system 100 includes a multi-core processor 110, a power supply circuit 120, a control unit 130, a clock signal generator 140, and a detection unit 150, wherein the multi-core processor 110 includes at least a first processing core 111 and a second processing core 111. Two processing cores 112 .

[0023] The multi-core processor 110 , power supply circuit 120 , control unit 130 , clock signal generator 140 , and detection unit 150 are all assembled on the motherboard (not shown) of the multi-core processor system 100 . The above-mentioned power supply circuit 120 is electrically connected to the first processing core 111 and the second processing core 112 of the multi-core processor 110 respectively, so as to provide the power required by these processing cores 111 , 112 . In this embodiment, the power supply circuit 120 can be realiz...

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Abstract

An efficiency regulation method for a multi-core processor is disclosed. A plurality of cores of the multi-core processor comprise at least a first processing core and a second processing core. The efficiency regulation method comprises following steps: (a) detecting multiplex degree of the multi-core processor and load of the processing cores to obtain a first detecting result; (b) according to the detecting result, judging whether the arithmetic bottleneck is centralized at one processing core of the a plurality of processing cores or not; (c) if the arithmetic bottleneck takes place at the first processing core, regulating main frequency of the first processing core based on the multiplex degree of the multi-core processor.

Description

technical field [0001] The present invention relates to a multi-core processor, and in particular to a method for adjusting performance of the multi-core processor. Background technique [0002] At present, many manufacturers are competing to develop related technologies of multi-core processors, making multi-core processors gradually become a market trend. [0003] However, the current multi-core processor system is even equipped with an operating system that supports multi-processors. If the application program can only be executed by a single program (Process) or a single thread (Thread) without being rewritten or recompiled, the application program will only be executed by a single processing core allocated therein. At this time, even if there is no other processing program to be executed, the other processing cores are just idle and will not speed up the execution of the calculation. Or, if the program is not optimized for multiprocessor architectures when it is writt...

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Application Information

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IPC IPC(8): G06F1/32G06F15/80
Inventor 朱少康
Owner ASUSTEK COMPUTER INC