Process and interrupt processing method and device for symmetrical multiprocessing system

Abstract

The invention discloses a disposal for process and interruption in a SMP system. The method adapts separation interrupt handling and process handling on processor grade, processes specially the interruption by using one or a group processors, furthermore, monitors the process and the interruption handling, and dynamic adjusts the number of processors in two group processors according to the load index of the process and the interruption handling. The invention also discloses a handling device for process and interruption in a SMP system. The device comprises interrupted handling module, a process processing module, a process and interruption monitor module. The device ensures the process handling and interruption handling mutual noninterference to improve the hit rate of cache and to ensure the stabilizing ability and actual time character of the system.

Description

technical field [0001] The invention relates to the field of symmetric multiprocessor systems, in particular to a process and interrupt processing method and device in the symmetric multiprocessor system. Background technique [0002] With the rapid development of multiprocessor technology, multiprocessor platforms are being more and more widely used in various fields such as industrial automation, electronic communication, and home appliances. At the same time, the processing of various process scheduling and interrupt sources on multi-processor platforms is becoming more and more complex. In this case, in order to ensure the stability and real-time performance of the multiprocessor platform in the process of process scheduling and interrupt handling, the original process scheduling and interrupt handling technology has also been continuously developed. [0003] Multiprocessing systems include symmetric multiprocessing systems and asymmetric multiprocessing systems. The i...

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Problems solved by technology

[0005] However, with the increasing number of interrupted devices and the increasing number of user processes, the existing multiprocessor system process scheduling and interrupt handling methods are facing various challenges in terms of stability and real-time performance.

First of all, since each processor handles interrupts and runs user processes, if a certain device interrupts too frequently, the processor must continuously enter the interrupt when executing the process, switch back to the process after the interrupt is processed, and start again and again. In the preemptive operating system, the CPU occupancy rate will remain at a high level, resulting in delays in process processing. Intuitively, the operating system is slow to respond to user input, which affects the real-time performance of the system.

Secondly, since the processes and interrupts are evenly distributed to each processor, frequent interrupts and more scheduled processes will frequently switch on the processor; because the cache always saves the data with high access rate or the running The data to be called by the program in the next step is stored in it. If the job is switched frequently, for the processor cache, it is necessary to transfer the relevant data involved in the operation interruption and the relevant data involved in the running process. Frequent switching, which is a disaster for the processor's cache, will not guarantee a high hit rate, and in some cases will seriously affect the stability and real-time performance of the system

[0006] In the existing Chinese patent application with application number CN200710066924 "Process Scheduling Method for Heterogeneous Multi-Core Systems", because the patent application puts interrupts and processes on the same core for processing, it is unavoidable when the number of processes is large and interrupts are frequent. In the case of frequent switching, the system overhead caused by frequent switching affects the real-time performance of the system to a certain extent.

[0007] The U.S. patent application "Scheduling threads in a multi-processor computer" with the application number US20050246461 (scheduling threads among multi-processor CPUs), although in this patent, processes and interrupts are distributed in a balanced manner on multiple cores, but It cannot fundamentally solve the system overhead caused by frequent switching of processes and interrupts on the same core; therefore, in the case of various interrupt devices, complex interrupt processing, and a large number of processes, it will affect the real-time performance of the system's response to interrupts and processing processes

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